Flip chip in leaded molded package and method of manufacture thereof

• US 6,949,410 B2
• Filed: 06/27/2003
• Issued: 09/27/2005
• Est. Priority Date: 12/16/1999
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Joshi, Rajeev, Tangpuz, Consuelo N., Manatad, Romel N.
• Primary Examiner(s): Brewster, William M.
• Application Number:
  US10/607,633
• Publication Number:
  US 20040056364A1
• Time in Patent Office: 823 Days
• Field of Search: 438/111, 438/112, 438/116, 438/123, 438/124, 438/64
• US Class Current: 438/111
• CPC Class Codes: H01L 2223/54406 comprising alphanumeric information
• CPC Class Codes: H01L 2223/54433 containing identification or tracking information
• CPC Class Codes: H01L 2223/54486 Located on package parts, e.g. encapsulation, leads, package substrate
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3185 the coating covering also the sidewalls of the semiconductor body
• CPC Class Codes: H01L 23/49531 the additional leads being a wiring board
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.

Claims

1. A method of making a chip device, the method comprising:

providing a leadframe that includes leads;

providing a die that includes a backside, wherein the backside of the die forms a first electrical terminal;

coupling a frontside of the die to the leadframe with solder, wherein the frontside of the die comprises a second electrical terminal, wherein first electrical terminal and the second electrical terminal are terminals in a MOSFET device; and

encapsulating the die with a body such that the backside of the die is adjacent to a window defined within the body.

2. A method in accordance with claim 1 wherein after encapsulating, ends of the leads of the leadframe are substantially coplanar with the backside of the die.

3. A method in accordance with claim 2 further comprising removing dambars from the leadframe, removing mold flashes and resins from the leads, and solder plating the leads.

4. A method in accordance with claim 1 further comprising marking the body on a surface opposite the window.

5. A method in accordance with claim 4 wherein the marking is performed with a laser.

6. A method in accordance with claim 4 wherein the marking is performed with ink.

7. A method in accordance with claim 1 wherein the leadframe is provided with preplated leads.

8. A method in accordance with claim 1 wherein the leadframe is provided with preformed leads.

9. A method in accordance with claim 1 wherein the leadframe is provided with preplated leads and preformed leads.

10. A method in accordance with claim 1 wherein the die is coupled to the leadframe via solder bumps, and wherein the solder bumps are re-flowed.

11. A method in accordance with claim 1 wherein the die is a first die and wherein the method includes attaching a second die to the leadframe.

12. A method comprising:

providing a leadframe that includes leads;

providing a semiconductor die that includes a backside including a first electrical terminal and a frontside including a second electrical terminal, wherein the first electrical terminal and the second electrical terminal are terminals in an electrical device;

mounting the semiconductor die to the leadframe; and

encapsulating the semiconductor die and at least a portion of the leadframe with a molding compound having a window and an exterior surface, wherein the backside of the semiconductor die is exposed through the window of the molding compound and wherein the backside is substantially flush with the exterior surface of the molding compound.

13. The method of claim 12 wherein the electrical device is a power transistor.

14. The method of claim 12 further comprising:

mounting a second semiconductor die including a second backside to the leadframe, wherein second backside is exposed through a second window in the molding compound.

15. The method of claim 12 wherein mounting the semiconductor die to the leadframe includes using solder to mount the semiconductor die to the leadframe.

16. The method of claim 12 wherein the second electrical terminal is a source or gate terminal at the frontside.

17. The method of claim 12 wherein the leadframe is pre-plated.

18. The method of claim 12 wherein ends of the leads are co-planar with the backside of the semiconductor die.

19. The method of claim 12 wherein the backside of the semiconductor die is metallized.

20. The method of claim 12 wherein the device is a MOSFET, and wherein the backside forms a drain terminal of the MOSFET in the die.