Method of forming a vertical MOS transistor

• US 6,949,421 B1
• Filed: 06/29/2004
• Issued: 09/27/2005
• Est. Priority Date: 11/06/2002
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Yegnashankaran, Visvamohan, Padmanabhan, Gobi R.
• Primary Examiner(s): Blum, David S.
• Application Number:
  US10/880,296
• Time in Patent Office: 455 Days
• Field of Search: 438250-253, 438240-243, 438/149, 438/156, 438/157
• US Class Current: 438/156
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A vertical MOS transistor has a very short channel length that is indirectly defined by the thickness of a layer of semiconductor material or the depths of implants. The transistor has a first (source/drain) region formed in a substrate material, a semiconductor region formed on the first region, and a second (source/drain) region formed in the top surface of the semiconductor region. The distance between the first region and the second region defines the channel length of the transistor.

Claims

1. A method of forming a MOS transistor in a semiconductor material of a first conductivity type, the method comprising the steps of:

forming a first region of a second conductivity type in the semiconductor material;

forming a semiconductor region of the first conductivity type on the semiconductor material, the semiconductor region having a first side wall, an opposite second side wall, and a top surface;

forming a layer of insulation material on the semiconductor material adjacent to the semiconductor region;

forming a layer of conductive material on the layer of insulation material;

removing substantially all of the layer of conductive material that lies vertically over the first region; and

etching the layer of conductive material to form a first gate and a second gate on the layer of insulation material, the first and second gates being on opposite sides of the semiconductor region.

2. The method of claim 1 wherein the semiconductor region is formed over the first region.

3. The method of claim 1 wherein the first region is formed by implanting dopants through the semiconductor region.

4. The method of claim 1 and further comprising the step of forming a second region in the top surface of the semiconductor region.

5. The method of claim 1 wherein the first region has a substantially uniform dopant concentration.

6. The method of claim 4 wherein the second region has a substantially uniform dopant concentration.

7. The method of claim 1 wherein the first region has a substantially non-uniform dopant concentration, and includes:

a surface region of a light dopant concentration; and

a lower region of a heavy dopant concentration that lies below and contacts the surface region.

8. The method of claim 4 wherein the second region has a substantially non-uniform dopant concentration, and includes:

a surface region of a heavy dopant concentration; and

a lower region of a light dopant concentration that lies below and contacts the surface region.

9. The method of claim 4 wherein a distance between the first region and the second region defines a channel length of the transistor.

10. The method of claim 1 and further comprising the steps of:

forming a layer of silicon germanium on the semiconductor region; and

forming a layer of silicon on the layer of silicon germanium, the layer of insulation material being formed on a part of the layer of silicon.

11. The method of claim 1 wherein the semiconductor material is formed on a layer of insulation material, the first region contacting the layer of insulation material.

12. A method of forming a MOS transistor in a semiconductor segment of a first conductivity type, the method comprising the steps of:

implanting the semiconductor segment to form an implanted region of a second conductivity type, the implanted region having a top surface;

forming a layer of semiconductor material on the semiconductor segment to contact the top surface of the implanted region, the layer of semiconductor material having the first conductivity type;

etching the layer of semiconductor material to form a semiconductor region that contacts and lies vertically over substantially all of the implanted region;

forming an isolation layer over the semiconductor segment after the layer of semiconductor material has been formed and after the layer of semiconductor material has been etched; and

forming a gate on the isolation layer.

13. The method of claim 12 and further comprising the step of implanting the semiconductor region to form a doped region of the second conductivity type, the doped region being spaced apart from the implanted region.

14. The method of claim 13 wherein the isolation layer contacts the semiconductor region.

15. A method of forming a MOS transistor in a semiconductor segment of a first conductivity type, the method comprising the steps of:

implanting the semiconductor segment to form an implanted region of a second conductivity type, the implanted region having a top surface, the implanted region lying below a top surface of the semiconductor segment;

etching the semiconductor segment until a top surface of the semiconductor segment and the top surface of the implanted region lie in substantially a same plane to form a semiconductor region that contacts and lies over the implanted region before the isolation layer is formed;

forming an isolation layer over the semiconductor segment; and

forming a gate on the isolation layer.

16. The method of claim 15 and further comprising the step of implanting the semiconductor region to form a doped region of the second conductivity type, the doped region being spaced apart from the implanted region.

17. The method of claim 16 wherein the isolation layer contacts the semiconductor region.

18. The method of claim 15 and further comprising the step of forming a layer of semiconductor material over the semiconductor region, the layer of semiconductor material including germanium and contacting the semiconductor region.

19. The method of claim 18 wherein the isolation layer contacts the layer of semiconductor material.