Differential capacitance measurement
First Claim
1. A circuit, capable of evaluating small variations in magnitude of capacitance within a differential capacitor arrangement forming a transducer and thus apt for real-time evaluating and measuring said differential capacitive transducers with high sensitivity and great noise immunity, implemented as a pair of sensor capacitors, connected normally to the two input terminals of said circuit and delivering a precise and stable output signal as result of said measurement to its output terminals, comprising:
- capacitive sensor elements or transducers in form of capacitors, connected to input terminals of evaluation means and designated as transducer capacitors;
means for evaluating said small variations in magnitude of capacitance in real-time and thus measuring said capacitive sensor elements, delivering output signals as result of said measurement and consisting of some means for charging and discharging said transducer capacitors with charges delivered by appropriate supply voltages, means for transferring and exchanging said charges implemented in form of a switching network, and means for transforming said transferred and applicatively exchanged charges into voltages equivalent to said output signals implemented within read-out system;
means for internal intermediate storage of electrical energy, assembled as a four-pole (two-port) circuit exhibiting two input and two output terminals; and
amplifier stages connected to said output terminals of said means for internal intermediate storage of electrical energy, delivering a boosted output signal at the output terminals of the circuit.
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Accused Products
Abstract
A circuit and method are given, which realizes a stable yet sensitive differential capacitance measuring device with good RF-suppression and with very acceptable noise features for use in capacitive sensor evaluation systems. By evaluating the difference of capacitor values only—with the help of a switched capacitor front-end—large spreads of transducer capacitor values are tolerable. Furthermore a mode of operation can be set up, where no essential galvanic connection between sensor input and the active read-out input at any given time is existing. The solution found exhibits a highly symmetrical construction. Using the intrinsic advantages of that solution the circuit of the invention is manufactured as an integrated circuit with standard CMOS technology at low cost.
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Citations
50 Claims
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1. A circuit, capable of evaluating small variations in magnitude of capacitance within a differential capacitor arrangement forming a transducer and thus apt for real-time evaluating and measuring said differential capacitive transducers with high sensitivity and great noise immunity, implemented as a pair of sensor capacitors, connected normally to the two input terminals of said circuit and delivering a precise and stable output signal as result of said measurement to its output terminals, comprising:
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capacitive sensor elements or transducers in form of capacitors, connected to input terminals of evaluation means and designated as transducer capacitors; means for evaluating said small variations in magnitude of capacitance in real-time and thus measuring said capacitive sensor elements, delivering output signals as result of said measurement and consisting of some means for charging and discharging said transducer capacitors with charges delivered by appropriate supply voltages, means for transferring and exchanging said charges implemented in form of a switching network, and means for transforming said transferred and applicatively exchanged charges into voltages equivalent to said output signals implemented within read-out system; means for internal intermediate storage of electrical energy, assembled as a four-pole (two-port) circuit exhibiting two input and two output terminals; and amplifier stages connected to said output terminals of said means for internal intermediate storage of electrical energy, delivering a boosted output signal at the output terminals of the circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37)
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38. A circuit, capable of evaluating small variations in magnitude of capacitance within a differential capacitor arrangement forming a transducer and thus apt for real-time evaluating and measuring said differential capacitive transducers with high sensitivity and great noise immunity, implemented as a pair of sensor capacitors, connected normally to the two input terminals of said circuit and delivering a precise and stable output signal as result of said measurement to its output terminals, comprising:
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capacitive sensor elements or transducers in form of capacitors, connected to said input terminals of said circuit and designated as transducer capacitors; two input terminals for connecting said two capacitive sensor elements designated as transducer capacitors; two supply voltage terminals for connecting appropriate positive and negative supply voltages; one virtual ground terminal for connecting to a reference potential; two output terminals for delivering said output signal as result of said measurement; two internal storage capacitors for the intermediate storage of the difference of charges from said transducer capacitors; two pairs of switches for connecting said two transducer capacitors to said positive and negative supply voltages, whereby each transducer capacitor is separately and alternatively being connected to either said positive or said negative supply voltage; two pairs of switches for connecting said capacitive sensor elements to said two internal storage capacitors;
whereby both transducer capacitors are commonly but alternatively being connected to either the first internal storage capacitor or the second internal storage capacitor;one ‘
difference’
capacitor for the summing up of the charges from said two internal storage capacitors onto said ‘
difference’
capacitor;one pair of switches for connecting said two internal storage capacitors to said ‘
difference’
capacitor;one pair of switches for connecting said ‘
difference’
capacitor with its appearing output voltage to two internal terminals;one amplifier stage connected to said two internal terminals and implemented as a multiple stage amplifier, which starts with a differential amplifier stage as a differential operational amplifier and ends with an impedance converter stage as a non-inverting operational amplifier, delivering said precise and stable output signal. - View Dependent Claims (39, 40, 41, 42, 43, 44, 45, 46, 47)
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48. A method for differential capacitance measurements, capable of evaluating small capacitance variations within a differential capacitor arrangement forming a transducer and thus apt for real-time evaluation and measurement of said differential capacitive transducers with high sensitivity and great noise immunity, comprising:
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providing a sensor element with at least two variable transducer capacitors configured as a differential capacitor for an evaluation by the following measurement procedure; providing a means for a real-time evaluation of the operational variations of said transducer capacitor values in form of a switched capacitor (SC) front-end deploying two input terminals for connecting said transducer capacitors and two output terminals for delivering an appropriate output signal as result of the evaluation measurement; providing appropriate supply voltages for said means; providing—
within said SC front-end—
as switched charge exchange network a general switching circuit part for generating charges, charge transfer and charge exchange;providing a means for the post processing of said output signal in form of amplifier stages for level and reference conversion, buffering and boosting of said output signal; making available—
within said SC front-end—
said appropriate supply voltages for charging each of said transducer capacitors with the help of two appropriate pairs of switches belonging to said switched charge exchange network;making available—
within said SC front-end—
a pair of internal storage capacitors together with two appropriate pairs of switches—
also belonging to said switched charge exchange network—
for transport of charges from said transducer capacitors to said internal storage capacitors;making available—
within said SC front-end—
a read-out system with input and output terminals—
which, together with two optionally and appropriately used switches is capable of interpreting said stored charge on said internal storage capacitors thus preparing the delivery of said output signal as result of said evaluation measurement;establishing a periodic timing schedule (comprising at least three separate time segments each again separable in some number of time slots) for the pertinent operation of the switches within said SC front-end for said charging of said transducer capacitors in time segment I, for said charge transport from said transducer capacitors to said read-out system in time segment II and for said delivery and said interpreting of said output signal in time segment III; determining for said SC front-end the charging and discharging of both of said transducer capacitors by means of two pairs of switches with regard to said appropriate corresponding supply voltages; determining within said SC front-end the transport of charges from both of said transducer capacitors to said separate and respective internal storage capacitors by means of two pairs of switches; determining within said SC front-end the transport of charges from both of said internal storage capacitors to said input terminals of said read-out system by some means, thus establishing an input voltage for said read-out system; determining within said read-out system the conversion of said input voltage at said input terminals into an output voltage at said output terminals, thus producing said output voltage for said SC front-end; executing the charging of the first of said transducer capacitors and the discharging of the second of said transducer capacitors by means of the first pair of said switches with regard to said appropriate corresponding supply voltages e.g. during a slot in time segment I; executing the transport of charges from both of said transducer capacitors to the first of said separate internal storage capacitors by means of the first pair of said switches during a slot in time segment I; executing the discharging of the first of said transducer capacitors and the charging of the second of said transducer capacitors by means of the second pair of said switches with regard to said appropriate corresponding supply voltages e.g. during a slot in time segment II; executing the transport of charges from both of said transducer capacitors to the second of said separate internal storage capacitors by means of the second pair of said switches during a slot in time segment II; restarting optionally the execution of the timing schedule from the beginning with segment I and repeat the according processing steps during time segments I and II continuously until a terminating condition is reached; executing the transport of charges from both of said internal storage capacitors to said input terminals of said read-out system by some means, thus establishing an input voltage for said read-out system e.g. during time segment III; executing within said read-out system the conversion of said input voltage at said input terminals into an output voltage at said output terminals, thus producing said output voltage for said SC front-end e.g. during time segment III, and thus furnishing a floating output voltage signal as said result of said evaluation measurement; restarting the execution of the timing schedule from the beginning with segment I and repeat the according processing steps e.g. during time segments I, II and III continuously; conditioning said floating output voltage signal as said result of said evaluation measurement at said output terminals continuously by amplifying the difference of said floating voltages within a first amplifier stage of said amplifier stages for said level and reference conversion; and conditioning further on the output voltage signal of said first amplifier stage of said amplifier stages for said buffering and boosting of said output signal continuously in a second single ended amplifier stage thus resulting in a final gain adjusted strong output signal of said difference capacitance measurement.
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49. A method for differential capacitance measurements, capable of evaluating small capacitance variations within a differential capacitor arrangement forming a transducer and thus apt for real-time evaluation and measurement of said differential capacitive transducers with high sensitivity and great noise immunity, comprising:
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providing a sensor element with at least two variable transducer capacitors configured as a differential capacitor for an evaluation by the following measurement procedure; providing a means for a real-time evaluation of the operational changes of said transducer capacitor values in form of a switched capacitor (SC) front-end deploying two input terminals for connecting said transducer capacitors and two output terminals for delivering an appropriate floating output signal as result of said evaluation measurement; providing appropriate supply voltages for said means; providing a means for the post processing of said output signal in form of amplifier stages for level and reference conversion, buffering and boosting of said output signal; making available—
within said SC front-end—
appropriate supply voltages for charging each of said transducer capacitors with the help of two appropriate pairs of switches;making available—
within said SC front-end—
a pair of internal storage capacitors together with two appropriate pairs of switches for transport of charges from said transducer capacitors to said internal storage capacitors;making available—
within said SC front-end—
a ‘
difference’
capacitor together with two appropriate pairs of switches for loading and unloading said ‘
difference’
capacitor thus delivering said output signal as result of the evaluation measurement;establishing a periodic timing schedule (consisting of three separate time segments) for the pertinent operation of the switches within said SC front-end for said charging of said transducer capacitors—
in time segment I—
, for said charge transport from said transducer capacitors to said internal storage capacitors—
in time segment II and for said loading and unloading of said internal ‘
difference’
capacitor—
in time segment III;determining for said SC front-end the charging and discharging of both of said transducer capacitors by means of two pairs of switches with regard to said appropriate corresponding supply voltages; determining within said SC front-end the transport of charges from both of said transducer capacitors to said separate and respective internal storage capacitors by means of two pairs of switches; determining within said SC front-end the transport of charges from both of said internal storage capacitors to said one internal ‘
difference’
capacitor by means of one pair of switches, thus loading said internal ‘
difference’
capacitor;determining within said SC front-end the transfer of charge from said one internal ‘
difference’
capacitor by means of one pair of switches to said output voltage terminals, thus unloading said internal ‘
difference’
capacitor;executing the charging of the first of said transducer capacitors and the discharging of the second of said transducer capacitors by means of the first pair of said switches with regard to said appropriate corresponding supply voltages during time segment I; executing the transport of charges from both of said transducer capacitors to the first of said separate internal storage capacitors by means of the first pair of said switches during time segment I; executing the discharging of the first of said transducer capacitors and the charging of the second of said transducer capacitors by means of the second pair of said switches with regard to said appropriate corresponding supply voltages during time segment II; executing the transport of charges from both of said transducer capacitors to the second of said separate internal storage capacitors by means of the second pair of said switches during time segment I1; executing the transport of charges from both of said internal storage capacitors to said one internal ‘
difference’
capacitor by means of said one pair of switches, thus loading said internal ‘
difference’
capacitor during time segment III;executing the transfer of charge from said one internal ‘
difference’
capacitor by means of said one other pair of switches to said output voltage terminals, thus unloading said internal ‘
difference’
capacitor during time segment III, and thus furnishing a floating output voltage signal as said result of said evaluation measurement;restarting the execution of the timing schedule from the beginning with segment I and repeating the according processing steps during time segments I, II and III continuously; conditioning said floating output voltage signal as said result of said evaluation measurement at said output terminals continuously by amplifying the difference of said floating voltages within a first amplifier stage of said amplifier stages for said level and reference conversion; and conditioning further on the output voltage signal of said first amplifier stage of said amplifier stages for said buffering and boosting of said output signal continuously in a second single ended amplifier stage thus resulting in a final gain adjusted strong output signal of said difference capacitance measurement. - View Dependent Claims (50)
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Specification