Device for measurement and analysis of electrical signals of an integrated circuit component

• US 6,949,940 B2
• Filed: 12/18/2000
• Issued: 09/27/2005
• Est. Priority Date: 06/16/1998
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Infineon Technologies AG
• Inventors: Dörrhöfer, Carsten, Schmid, Wilhelm
• Primary Examiner(s): Cuneo, Kamand
• Assistant Examiner(s): PATEL, PARESH H
• Application Number:
  US09/740,634
• Publication Number:
  US 20010052783A1
• Time in Patent Office: 1,744 Days
• Field of Search: 324/763, 324/765, 714733-734, 257/48
• US Class Current: 324/750.3
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: G01R 31/31708 Analysis of signal quality G01R31/31901 takes precedence; measuring frequencies or analysing frequency spectra per se G01R23/00; measuring non-linear distortion per se G01R23/20
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G01R 31/318572 Input/Output interfaces
• CPC Class Codes: G01R 31/31926 Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing

Abstract

According to the invention, one or more external test connection contact points (pads; pins; balls), are provided in an integrated circuit component (chip) (1), through which signals (4, 5, 6) that are to be measured or analyzed are selectively fed, e.g. by means of a multiplex circuit (7, 8), and wherein the signals may be connected by means of routes located internally in the component from switch points that are not directly accessible, e.g. points inside the chip (15 to 20) or covered contact points. The device according to the invention is particularly useful for highly integrated semiconductor chips.

Claims

1. An integrated circuit component, comprising:

a plurality of circuit points not being directly externally accessible, providing a reference signal provided by the integrated circuit component for test purposes, and various electrical signals of the integrated circuit component to be monitored for test purposes;

at least one connecting contact point being externally accessible; and

a multiplexer having an output connected to said at least one connecting contact point and having a plurality of inputs, each one of said plurality of inputs being connected to a respective one of said plurality of circuit points, permitting external access to the reference signal and to the various electrical signals.

2. The integrated circuit component according to claim 1, wherein

said at least one connecting contact point is one of a plurality of connecting contact points.

3. The integrated circuit component according to claim 2, wherein said plurality of connecting contact points is exactly two connecting contact points.

4. The integrated circuit component according to claim 3, further comprising a second multiplexing circuit.

5. The integrated circuit component according to claim 4, wherein said multiplexing circuit is programmably controlled to predetermine selective passing on of the electrical signals to said at least one connecting contact point.

6. The integrated circuit component according to claim 1, wherein:

said electrical signals are internal chip signals in the integrated circuit component, and said reference signal are used for monitoring the timing of said internal chip signals.

7. The integrated circuit according to claim 1, comprising a package and wherein:

said plurality of contact points are disposed on said package.

8. The integrated circuit according to claim 7, wherein:

said package is a ball grid array package having a lower face;

said plurality of inaccessible contact points are located on said lower face of said package and are thus concealed between said package and a system board on which said package is fitted; and

said at least one connecting contact point is electrically conductively connected to a corresponding number of metallic test points on the system board.

9. The integrated circuit according to claim 1, wherein:

said multiplexing circuit is time-controlled and is provided in the integrated circuit component surrounded by a ball grid array package.

10. The integrated circuit component according to claim 1, wherein said at least one connecting contact point can be selectively used in an opposite operating direction for inputting signals to said plurality of circuit points that are not externally accessible.

11. The integrated circuit according to claim 1, wherein said at least one connecting contact point is connected to a component tester for analyzing the electrical signals.

12. The integrated circuit component according to claim 1, wherein said at least one connecting contact point is connected to a system analyzer and an application of said system analyzer analyzes the electrical signals of, at least some of said plurality of circuit points.

13. An integrated circuit component, comprising:

a first plurality of circuit points of the integrated circuit component not being directly externally accessible, providing a reference signal provided by the integrated circuit component for test purposes;

a second plurality of circuit points of the integrated circuit not being directly externally accessible, providing electrical signals of the integrated circuit component to be monitored for test purposes;

a first connecting contact point being externally accessible;

a second connecting contact point being externally accessible;

a first multiplexer having an output connected to said first connecting contact point and having a plurality of inputs, each one of said plurality of inputs being connected to a respective one of said first plurality of circuit points, permitting external access to the reference signal;

a second multiplexer having an output connected to said second connecting contact point and having a plurality of inputs, each one of said plurality of inputs being connected to a respective one of said second plurality of circuit points, permitting external access to the various electrical signals.