Phase comparator capable of tolerating a non-50% duty-cycle clocks

• US 6,949,958 B2
• Filed: 10/28/2002
• Issued: 09/27/2005
• Est. Priority Date: 10/10/1997
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Barth, Richard M., Davis, Paul G., Abhyankar, Abhijit M., Stonecypher, William F., Chan, Andy Peng-Pui, Zerbe, Jared LeVan, Ching, Michael Tak-kei
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Nguyen, Hai L.
• Application Number:
  US10/282,531
• Publication Number:
  US 20030053489A1
• Time in Patent Office: 1,065 Days
• Field of Search: 327/2, 327/3, 327 7- 9, 327/12, 327 39- 49, 327144-147, 327/162, 327154-156, 327/99, 331/25, 324/76.77, 324/76.78, 324/76.82, 375/373, 375/375, 375/376
• US Class Current: 327/3
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 13/423 with synchronous protocol
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H04L 7/0012 by comparing receiver clock with transmitter clock
• CPC Class Codes: H04L 7/0045 Correction by a latch cascade
• CPC Class Codes: H04L 7/0054 Detection of the synchronisation error by features other than the received signal transition by means of signal transition H04L7/033
• CPC Class Codes: H04L 7/02 Speed or phase control by the received code signals, the signals containing no special synchronisation information H04L7/0075 takes precedence
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.

Claims

1. A phase comparator for use in conjunction with a clock domain crossing circuit, comprising:

a first sampling circuit for sampling a first clock with a first edge of second clock to produce a selection signal, wherein the first and second clocks are mesochronous;

a second sampling circuit for sampling a third clock having a fixed phase differential relative to the first clock to produce a first sample signal, the third clock being sampled with a second edge of the second clock, the second edge of the second clock having an opposite transition direction relative to the first edge of the second clock;

a third sampling circuit for sampling the third clock with the first edge of the second clock to produce a second sample signal; and

a multiplexer for selectly outputting one of the first and second sample signals in accordance with the selection signal to produce a phase comparison signal, wherein the phase comparison signal has a value that is determined by a phase difference between the first clock and the second clock.

2. The phase comparator of claim 1, wherein the third clock is in quadrature with the first clock.

3. The phase comparator of claim 1, the second sampling circuit including an inverter at an output of the second sampling circuit for inverting the sampled third clock.

4. The phase comparator of claim 1, further including an integrator for integrating the phase comparison signal to produce a phase comparator output signal.

5. The phase comparator of claim 4, further including a latch for latching the phase comparator output signal to produce a skip signal.