Correlation of electrical test data with physical defect data

• US 6,950,771 B1
• Filed: 12/09/2003
• Issued: 09/27/2005
• Est. Priority Date: 12/09/2003
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Xu, Jason, Tang, Stephen Wing-Ho, Fan, Yuezhen, Ling, Zhi-Min
• Primary Examiner(s): Barlow, John
• Assistant Examiner(s): Khuu, Cindy D.
• Application Number:
  US10/732,493
• Time in Patent Office: 658 Days
• Field of Search: 702/117, 702/33, 702/35, 702/36, 702/81, 702/82, 702/84
• US Class Current: 702/117
• CPC Class Codes: G01R 31/2894 Aspects of quality control [QC] G01R31/31718 takes precedence; program control for QC G05B19/41875
• CPC Class Codes: G01R 31/318566 Comparators; Diagnosing the device under test
• CPC Class Codes: G11C 2029/1806 Address conversion or mapping, i.e. logical to physical address
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair

Abstract

Method and apparatus are disclosed for analyzing defect data produced in testing a semiconductor chip from a logic design. In various embodiments, input for processing is a first inspection data set that identifies a first set of physical locations that are associated with defects detected during fabrication of the chip. Also input is a second test data set that includes one or more identifiers associated with failing circuitry in the chip. A second set of physical locations is determined from the one or more identifiers of failing circuitry, hierarchical relationships between blocks of the design, and placement information associated with the blocks. Each of the one or more identifiers is associated with at least one of the blocks. Correspondences are identified between physical locations in the first inspection data set and the second set of physical locations.

Claims

1. A computer-implemented method for analyzing defect data produced in testing a semiconductor chip from a logic design, comprising:

inputting a first data set that identifies a first set of physical locations associated with defects detected during fabrication of the chip;

inputting a second test data set that includes one or more identifiers associated with failing circuitry in the chip;

determining a second set of physical locations from the one or more identifiers of failing circuitry, hierarchical relationships between blocks of the logic design, and placement information associated with the blocks, wherein each of the one or more identifiers is associated with at least one of the blocks; and

identifying correspondences between physical locations in the first data set and the second set of physical locations.

2. The method of claim 1, wherein the first data set is in a first format further comprising:

formatting in a third test data set that is compatible with the first format of the first data set, data that indicate physical locations associated with defects described by the second test data set; and

comparing the first data set to the third test data set.

3. The method of claim 1, further comprising determining a block associated with the failing circuitry from a logic address if the failing circuitry is a memory cell.

4. The method of claim 1, further comprising determining a block associated with the failing circuitry from a circuit name if the failing circuitry is a circuit path.

5. The method of claim 1, further comprising:

determining for each identifier in the second test data set a block that is associated with the failing circuitry;

determining a position of the block;

determining at least one physical location in the second set of physical locations from placement information of ancestor blocks of the block.

6. The method of claim 5, further comprising determining the block associated with the failing circuitry from a logic address if the failing circuitry is a memory cell.

7. The method of claim 5, further comprising determining the block associated with the failing circuitry from a circuit name if the failing circuitry is a circuit path.

8. A method for testing a semiconductor chip, comprising:

inspecting the semiconductor chip for defects and storing an inspection data set that identifies a first set of physical locations associated with defects detected during inspection;

testing circuit paths on the semiconductor chip, and storing a test data set that includes one or more identifiers associated with failing circuitry in the semiconductor chip;

determining a second set of physical locations of defects described by the test data set from the one or more identifiers of failing circuitry, hierarchical relationships between blocks of a design, and placement information associated with the blocks, wherein each of the one or more identifiers is associated with at least one of the blocks; and

identifying correspondences between physical locations in the inspection data set and the second set of physical locations.

9. The method of claim 8, wherein at least a portion of the inspecting step is performed before fabrication of the semiconductor chip is complete.

10. The method of claim 8, wherein the inspection data set is in a first format further comprising:

formatting in a second test data set that is compatible with the first format of the inspection data set, data that indicate the physical locations in the second set; and

comparing the inspection data set to the second test data set.

11. The method of claim 8, further comprising determining a block associated with the failing circuitry from a logic address if the failing circuitry is a memory cell.

12. The method of claim 8, further comprising determining a block associated with the failing circuitry from a circuit name if the failing circuitry is a circuit path.

13. The method of claim 8, further comprising:

determining for each identifier in the test data set a first block that is associated with the failing circuitry;

determining the position of the first block;

determining each physical location in the second set of physical locations from placement information of ancestor blocks of the first block.

14. The method of claim 13, further comprising determining a block associated with the failing circuitry from a logic address if the failing circuitry is a memory cell.

15. The method of claim 13, further comprising determining a block associated with the failing circuitry from a circuit name if the failing circuitry is a circuit path.

16. An apparatus for analyzing defect data produced in testing a chip from a design, comprising:

means for inputting a first data set that identifies a first set of physical locations associated with defects detected during fabrication of the chip;

means for inputting a second test data set that includes one or more identifiers associated with failing circuitry in the chip;

means for determining a second set of physical locations from the one or more identifiers of failing circuitry, hierarchical relationships between blocks of the design, and placement information associated with the blocks, wherein each of the one or more identifiers is associated with at least one of the blocks; and

means for identifying correspondences between physical locations in the first data set and the second set of physical locations.