Mobile wireless communication device architectures and methods therefor
First Claim
Patent Images
1. A wireless communication architecture, comprising:
- a virtual channel memory controller;
first and second processor cores coupled to the virtual channel memory controller;
a first synchronous memory device coupled to the virtual channel memory controller by a dedicated first data bus;
a second synchronous memory device coupled to the virtual channel memory controller by a dedicated second data bus;
a shared address and control bus interconnecting the virtual channel memory controller and the first and second synchronous memory devices;
a group of shared memory space access registers defining access permission to shared memory space.
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Abstract
A wireless communications architecture having first and second synchronous memory devices coupled to a virtual channel memory controller by corresponding first and second data buses, and a shared address and control bus interconnecting the virtual channel memory controller and the first and second synchronous memory devices. The first and second synchronous memory devices are addressed with the shared address bus, and the first and second memory locations are accessed via the first and second data buses, respectively.
9 Citations
40 Claims
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1. A wireless communication architecture, comprising:
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a virtual channel memory controller;
first and second processor cores coupled to the virtual channel memory controller;
a first synchronous memory device coupled to the virtual channel memory controller by a dedicated first data bus;
a second synchronous memory device coupled to the virtual channel memory controller by a dedicated second data bus;
a shared address and control bus interconnecting the virtual channel memory controller and the first and second synchronous memory devices;
a group of shared memory space access registers defining access permission to shared memory space. - View Dependent Claims (2, 3, 5, 6, 7, 8, 24)
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4. A wireless communication architecture, comprising:
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a virtual channel memory controller;
first and second processor cores coupled to the virtual channel memory controller;
a first synchronous memory device coupled to the virtual channel memory controller by a dedicated first data bus;
a second synchronous memory device coupled to the virtual channel memory controller by a dedicated second data bus;
a shared address and control burn interconnecting the virtual channel memory controller and the first and second synchronous memory devices;
the virtual channel memory controller having a group of shared memory space access registers interconnecting first and second processor core memory access register blocks, the first processor core memory access register block coupled to the first processor core, the second processor core memory access register block coupled to the second processor core.
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9. A virtual channel shared memory architecture, comprising:
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a virtual channel memory controller;
a first synchronous memory device coupled to the virtual channel memory controller by a first data bus;
a second synchronous memory device coupled to the virtual channel memory controller by a second data bus;
a shared address and control bus interconnecting the virtual channel memory controller and the first and second synchronous memory devices;
wherein the virtual channel memory controller having a group of shared memory space access registers interconnecting first and second processor core memory access register blocks, the first processor core memory access register block coupled to the first processor core, the second processor care memory access register block coupled to the second processor core. - View Dependent Claims (10, 11)
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12. A method in a virtual channel shared memory system architecture, comprising:
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addressing first and second synchronous memory devices with a shared address bus interconnecting the first and second synchronous memory devices and a virtual channel memory controller;
accessing the first synchronous memory device via a first data bus interconnecting the first synchronous memory device and the virtual channel memory controller;
accessing the second synchronous memory device via a second data bus interconnecting the second synchronous memory device and the virtual channel memory controller;
conveying access permission to shared memory space with a group of registers indicating shared memory space policy, facilitating communication between first and second processor cores with shared memory space by passing data by reference. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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19. A method in a wireless communication architecture, comprising:
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addressing first and second synchronous memory devices with a shared address bus interconnecting the first and second synchronous memory devices and a virtual channel memory controller;
transferring data between the first synchronous memory device and the virtual channel memory controller on a first data bus;
transferring data between the second synchronous memory device and the virtual channel memory controller on a second data bus;
conveying access permission to shared memory space with a group of registers indicating shared memory space policy, facilitating communication between first and second processor cores with shared memory space by passing data by reference. - View Dependent Claims (20, 21, 22, 23)
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25. A wireless communication architecture, comprising:
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a virtual channel memory controller;
first and second processor cores coupled to the virtual channel memory controller;
a first synchronous memory device coupled to the virtual channel memory controller by a dedicated first data bus;
a second synchronous memory device coupled to the virtual channel memory controller by a dedicated second data bus;
a shared address and control bus interconnecting the virtual channel memory controller and the first and second synchronous memory devises;
a first processor core memory access register block coupled to the first processor core;
a second processor core memory access register block coupled to the second processor core;
wherein the first processor core memory access register block and the second processor core memory access register block define memory access permission and enforce protected memory areas of the first and second processor cores.
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26. A wireless communication architecture, comprising:
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a virtual channel memory controller;
first and second processor cores coupled to the virtual channel memory controller;
a first synchronous memory device coupled to the virtual channel memory controller;
a second synchronous memory device coupled to the virtual channel memory controller;
a shared address and control bus interconnecting the virtual channel memory controller and the first and second synchronous memory devices;
wherein the virtual channel memory controller and the first and second processor cores are disposed on a single integrated circuit;
a group of shared memory space access registers defining access permission to shared memory space, the group of shared memory space access registers disposed on the single integrated circuit. - View Dependent Claims (28, 29, 35, 36, 37)
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27. A wireless communication architecture, comprising:
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a virtual channel memory controller;
first and second processor cores coupled to the virtual channel memory controller;
a first synchronous memory device coupled to the virtual channel memory controller;
a second synchronous memory device coupled to the virtual channel memory controller;
a shared address and control bus interconnecting the virtual channel memory controller and the first and second synchronous memory devices;
wherein the virtual channel memory controller and the first and second processor cores are disposed on a single integrated circuit;
a first processor core memory access register block coupled to the first processor core, the first processor core memory access register block disposed on the single integrated circuit;
a second processor core memory access register block coupled to the second processor core, the second processor core memory access register block disposed on the single integrated circuit;
wherein the first processor core memory access register block and the second processor core memory access register block define memory access permission and enforce protected memory areas of the first and second processor cores.
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30. A wireless communication architecture, comprising:
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a virtual channel memory controller;
first and second processor cores coupled to the virtual channel memory controller;
a first synchronous memory device coupled to the virtual channel memory controller;
a second synchronous memory device coupled to the virtual channel memory controller;
a shared address and control bus interconnecting the virtual channel memory controller and the first and second synchronous memory devices;
wherein the virtual channel memory controller and the first and second processor cores are disposed on a single integrated circuit;
wherein in the virtual channel memory controller having a group of shared memory space access registers interconnecting first and second processor core memory access register blocks, the first processor core memory access register block coupled to the first processor core, the second processor core memory access register block coupled to the second processor core.
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31. A method in a virtual channel shared memory system architecture, comprising:
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addressing first and second synchronous memory devices with a shared address bus interconnecting the first and second synchronous memory devices and a virtual channel memory controller;
accessing the first synchronous memory device via a data bus interconnecting the first synchronous memory device and the virtual channel memory controller;
accessing the second synchronous memory device via a data bus interconnecting the second synchronous memory device and the virtual channel memory controller;
conveying access permission to shared memory space with a group of registers indicating shared memory space policy, facilitating communication between first and second processor cores with shared memory space by passing data by reference. - View Dependent Claims (32, 38, 39, 40)
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33. A method in a wireless communication architecture, comprising:
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addressing first and second synchronous memory devices with a shared address bus interconnecting the first and second synchronous memory devices and a virtual channel memory controller;
transferring data between the first synchronous memory device and the virtual channel memory controller;
transferring data between the second synchronous memory device and the virtual channel memory controller;
conveying access permission to shared memory space with a group of registers indicating shared memory space policy, facilitating communication between first and second processor cores with shared memory space by passing data by reference. - View Dependent Claims (34)
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Specification