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Mobile wireless communication device architectures and methods therefor

  • US 6,950,910 B2
  • Filed: 11/08/2001
  • Issued: 09/27/2005
  • Est. Priority Date: 11/08/2001
  • Status: Active Grant
First Claim
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1. A wireless communication architecture, comprising:

  • a virtual channel memory controller;

    first and second processor cores coupled to the virtual channel memory controller;

    a first synchronous memory device coupled to the virtual channel memory controller by a dedicated first data bus;

    a second synchronous memory device coupled to the virtual channel memory controller by a dedicated second data bus;

    a shared address and control bus interconnecting the virtual channel memory controller and the first and second synchronous memory devices;

    a group of shared memory space access registers defining access permission to shared memory space.

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