Computer system with operating system to dynamically adjust the main memory

• US 6,950,919 B2
• Filed: 03/26/2003
• Issued: 09/27/2005
• Est. Priority Date: 03/26/2003
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Sharma, Manish, Nickel, Janice H.
• Primary Examiner(s): GOODARZI, NASSER MOAZZAMI
• Application Number:
  US10/397,434
• Publication Number:
  US 20040193783A1
• Time in Patent Office: 916 Days
• Field of Search: 711/2, 711 5- 6, 711/104, 711/114, 711/115, 711/170, 711171-173, 711/203, 710 2- 3, 710 8- 10, 710/13, 710300-304, 714/7
• US Class Current: 711/170
• CPC Class Codes: G06F 9/4411 Configuring for operating with peripheral devices; Loading of device drivers
• CPC Class Codes: G06F 9/5016 the resource being the memory

Abstract

This disclosure provides a computer system with operating system permitting dynamic reallocation of main memory during operation. In a particular embodiment the computer system with operating system are used in connection with non-volatile main memory stores (NMS) such as MRAM. As the NMS is a component of main memory attached directly to the memory bus, the NMS functions at substantially the same speed as traditional volatile memory stores. Reallocation of main memory and use of applications or programs stored on the inserted NMS occurs at speeds orders of magnitude greater than traditional secondary memory devices.

Claims

1. A computer system comprising:

a main board;

at least one central processing unit (CPU) coupled to the main board;

a main memory, coupled to the at least one CPU by the main board, the main memory capable of receiving at least two memory stores comprising;

a first memory store (FMS); and

a removable non-volatile memory store (NMS), the NMS operating with the at least one CPU at the same speed as the FMS;

the main memory further capable of supporting an operating system loaded into the main memory upon power up of the computer system, the operating system controlling the primary operation of the at least one CPU and main memory, the operating system dynamically adjusting the main memory in response to the removal or insertion of the NMS;

at least one input device, coupled to the CPU; and

at least one output device, coupled to the CPU.

2. The computer system of claim 1, wherein the dynamic adjustment is in response to a notification regarding the removal or insertion of the NMS.

3. The computer system of claim 2, wherein the notification is a hardware interrupt response (IRQ), generated by the main board in response to the removal or insertion of the NMS.

4. The computer system of claim 1, further comprising a BIOS memory, coupled to the CPU by the main board, containing BIOS that registers a specific event to the system upon removal or insertion of the NMS.

5. The computer system of claim 4, wherein the NMS further comprises control signals for state and size of the NMS.

6. The computer system of claim 5, wherein the BIOS event is determined from the NMS control signals.

7. The computer system of claim 1, wherein the FMS is volatile RAM.

8. The computer system of claim 1, wherein the FMS is NMS.

9. The computer system of claim 1, wherein the NMS is magnetic random access memory (MRAM).

10. The computer system of claim 1, wherein the NMS is Ferroelectric random access memory (FeRAM).

11. A computer system comprising:

a main board;

at least one central processing unit (CPU) coupled to the main board;

a main memory, coupled to at least one CPU by the main board, comprising;

a first memory store (FMS);

a removable non-volatile memory store (NMS), the NMS operating with the at least one CPU at the same speed as the FMS; and

an operating system loaded into the FMS upon power up of the computer system, the operating system controlling the primary operation of the at least one CPU and main memory, the operating system dynamically adjusting the main memory in response to a notification regarding the removal or insertion of the NMS;

at least one input device, coupled to the at least one CPU; and

at least one output device, coupled to the at least one CPU.

12. The computer system of claim 11, wherein the notification is a hardware interrupt response (IRQ), generated by the main board in response to the removal or insertion of the NMS.

13. The computer system of claim 11, further comprising a BIOS memory, coupled to the CPU by the main board, containing BIOS that registers a specific event to the system upon removal or insertion of the NMS.

14. The computer system of claim 13, wherein the NMS further comprises control signals for state and size of the NMS.

15. The computer system of claim 14, wherein the BIOS event is determined from the NMS control signals.

16. The computer system of claim 13, wherein the notification is the specific event registered to the system by the BIOS.

17. The computer system of claim 11, wherein the FMS is volatile RAM.

18. The computer system of claim 11, wherein the FMS is NMS.

19. The computer system of claim 11, wherein the NMS is magnetic random access memory (MRAM).

20. The computer system of claim 11, wherein the NMS is Ferroelectric random access memory (FeRAM).

21. An operating system, executable by a computer having a CPU and memory, comprising:

a process manager for managing access time to the CPU for an active process;

a memory manager for managing memory comprising cache, main memory and virtual memory, for the execution of a currently active process by the CPU;

a device manager for managing the input and output of information required by a process as executed by the CPU; and

a main memory controller coupled to the memory manager, for dynamically adjusting use of main memory as non-volatile main memory is added or removed from the computer system during operation.

22. The operating system of claim 21, wherein the dynamic adjustment of use is upon a main memory comprising:

a first memory store (FMS); and

a removable non-volatile memory store (NMS), the NMS operating at the same speed as the FMS.

23. The operating system of claim 21, wherein the process may be a thread.

24. The operating system of claim 21, wherein the main memory controller dynamically adjusts use of main memory based upon a hardware interrupt (IRQ) generated by the hardware system.

25. The operating system of claim 21, wherein the main memory controller dynamically adjusts use of main memory based upon a BIOS event registered to the system.

26. The operating system of claim 21, wherein the operations of the main memory controller are given the highest priority by the process manager.

27. The operating system of claim 26, wherein the priority is absolute.

28. The operating system of claim 21, wherein the FMS is volatile RAM.

29. The operating system of claim 21, wherein the FMS is NMS.

30. The operating system of claim 21, wherein the non-volatile main memory is magnetic random access memory (MRAM).

31. The operating system of claim 21, wherein the non-volatile main memory is Ferroelectric random access memory (FeRAM).

32. A method of using an operating system having a process controller, memory manager, device manager, and a main memory controller to dynamically adjust use of a memory address pool when a non-volatile memory store (NMS) is inserted into the main memory store of an operating computer system having a NMS compliant hardware subsystem, comprising:

inserting the NMS into the computer system;

initializing the inserted NMS;

triggering a notification by the hardware subsystem that NMS has been initialized;

recognizing the notification within the operating system;

engaging the main memory controller, the main memory controller informing the process manager that memory reconfiguration is the highest priority;

polling the NMS to confirm a compliant memory structure for use with the main memory address pool; and

updating the main memory address pool to include the NMS memory structure.

33. The method of claim 32, wherein the notification is an IRQ event.

34. The method of claim 33, wherein the IRQ event is recorded by a BIOS flag.

35. The method of claim 34, wherein the recognition of the notification by the operating system is by the operating system polling the BIOS flag.

36. The method of claim 32, wherein the dynamic adjustment of use is upon a main memory store comprising:

a first memory store (FMS); and

a removable NMS, the NMS operating at the same speed as the FMS.

37. A method of using an operating system having a process controller, memory manager, device manager, and a main memory controller to dynamically adjust use of a memory address pool when a non-volatile memory store (NMS) is removed from the main memory store of an operating computer system having a NMS compliant hardware subsystem, comprising:

signaling the operating system the desire to remove the NMS;

engaging the main memory controller, the main memory controller informing the process manager that memory reconfiguration is the highest priority;

polling the memory manager for identification of NMS addresses tied to necessary memory data;

moving identified necessary data from NMS to remaining memory addresses; and

updating the main memory address pool to exclude the NMS memory addresses.

38. The method of claim 37, wherein the notification is an IRQ event.

39. The method of claim 37, further comprising increasing virtual memory to facilitate moving identified necessary data form NMS.

40. The method of claim 37, further comprising including a signal to the user that NMS may be safely removed.

41. The method of claim 37, wherein the dynamic adjustment of use is upon a main memory store comprising:

a first memory store (FMS); and

a removable NMS, the NMS operating at the same speed as the FMS.