Integrated circuit with timing adjustment mechanism and method

• US 6,950,956 B2
• Filed: 11/03/2003
• Issued: 09/27/2005
• Est. Priority Date: 10/19/1999
• Status: Expired due to Term

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Sidiropoulos, Stefanos, Kim, Jun, Stark, Donald C., Garlepp, Bruno W., Horowitz, Mark A., Donnelly, Kevin S., Yu, Leung, Lau, Benedict Chung-Kwong, Vu, Roxanne, Zerbe, Jared LeVan, Ho, Tsyr-Chyang
• Primary Examiner(s): Cottingham, John R.
• Assistant Examiner(s): Patel, Nitin C.
• Application Number:
  US10/700,655
• Publication Number:
  US 20040098634A1
• Time in Patent Office: 694 Days
• Field of Search: 713/400, 713/500, 713/503, 713/600, 713/375, 713/401, 327/141, 327/147, 327/233, 327/258, 327/2, 327/9, 375/146, 375/147, 375/316, 375/354, 375/355, 375/149, 375/219, 375/240.21, 710/69, 710/70, 710/107
• US Class Current: 713/400
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/404 with address mapping
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

An integrated circuit device includes a receiver, a register and a clock circuit. The receiver samples data from an external signal line in response to an internal clock signal. The register stores a value that represents a timing offset to adjust the time at which the data is sampled. The clock circuit generates the internal clock signal such that the internal clock signal maintains a controlled timing relationship with respect to an external clock signal. The clock circuit includes an interpolator that phase mixes a set of reference clock signals such that the internal clock signal is phase offset in accordance with the value.

Claims

1. An integrated circuit device comprising:

a receiver configured to sample data from an external signal line in response to an internal clock signal;

a register configured to store a value that represents a timing offset to adjust the time at which the data is sampled; and

a clock circuit configured to generate the internal clock signal such that the internal clock signal maintains a controlled timing relationship with respect to an external clock signal, the clock circuit including an interpolator, coupled to the register, to phase mix a set of reference clock signals such that the internal clock signal is phase offset in accordance with the value.

2. The device of claim 1, wherein the clock circuit includes a reference loop circuit that generates the set of reference clock signals.

3. The device of claim 2, wherein

the interpolator comprises a first interpolator, the internal clock signal comprises a first internal clock signal, and the clock circuit further includes a second interpolator configured to generate a second internal clock signal, wherein both the first interpolator and the second interpolator are coupled to the reference loop circuit so as to receive the set of reference clock signals;

the clock circuit further includes a phase adjustment circuit configured to compare a phase of the external clock with a phase of the second internal clock signal and to generate a phase adjustment value, wherein the second interpolator is configured to receive the phase adjustment value and to adjust the phase of the second internal signal in accordance with the phase adjustment value; and

the first interpolator is configured to generate the first internal clock signal in accordance with the phase adjustment value and the value stored by the register.

4. The device of claim 3, including an offset adjustment circuit configured to combine the phase adjustment value and the value stored by the register to produce an offset value;

wherein the first interpolator is configured to generate the first internal clock signal in accordance with offset value.

5. The device of claim 4, wherein the offset adjustment circuit includes an adder circuit.

6. The device of claim 2, wherein

the internal clock signal comprises a first internal clock signal;

the interpolator is configured to generate a second internal clock signal; and

the clock circuit includes a first clock buffer that is configured to receive the second internal clock signal and to generate a feedback signal, and a second clock buffer that is configured to receive the second internal clock signal and to generate the first internal clock signal.

7. The device of claim 6, wherein

the reference loop circuit is configured to generate a control signal;

and

the first clock buffer and the second clock buffer are configured to receive the control signal and to operate in accordance with the control signal.

8. The device of claim 7, wherein

the clock circuit further includes a phase adjustment circuit configured to compare a phase of the external clock with a phase of the feedback signal and to generate a phase adjustment value, wherein the interpolator is configured to receive the phase adjustment value and to adjust the phase of the second internal signal in accordance with the phase adjustment value.

9. The device of claim 8, wherein

the first clock buffer is coupled to the register and is configured to generate the feedback signal in accordance with the second internal clock signal, the control signal and the value stored by the register.

10. A method of operating an integrated circuit comprising:

sampling data from an external signal line in response to an internal clock signal;

establishing a value that represents a timing offset to adjust the time at which the data is sampled; and

generating the internal clock signal such that the internal clock signal maintains a controlled timing relationship with respect to an external clock signal, including phase mixing a set of reference clock signals in accordance with the established value such that the internal clock signal is phase offset in accordance with the established value.

11. The method of claim 10, including generating the set of reference clock signals using a reference loop circuit.

12. The method of claim 11, wherein

the internal clock signal comprises a first internal clock signal;

and

the method includes;

generating a second internal clock by phase mixing the set of reference clock signals;

comparing a phase of the external clock with a phase of the second internal clock signal and generating a phase adjustment value;

adjusting the phase of the second internal signal in accordance with the phase adjustment value; and

generating the first internal clock signal in accordance with the phase adjustment value and the established value.

13. The method of claim 12, including combining the phase adjustment value and the established value to produce an offset value, and generating the first internal clock signal in accordance with offset value.

14. The method of claim 13, including adding the phase adjustment value and the established value to produce the offset value.

15. The method of claim 11, wherein

the internal clock signal comprises a first internal clock signal;

and

the method includes;

generating a second internal clock signal; and

passing the second internal clock signal through a first clock buffer to generate a feedback signal; and

pass the second internal clock signal through a second clock buffer to generate the first internal clock signal.

16. The method of claim 15, wherein

generating a control signal using the reference loop circuit;

using the control signal to control operation of the first clock buffer and the second clock buffer.

17. The method of claim 16, wherein

comparing a phase of the external clock with a phase of the feedback signal and generating a phase adjustment value;

and

adjusting the phase of the second internal signal in accordance with the phase adjustment value.

18. The method of claim 17, including generating the feedback signal in accordance with the second internal clock signal, the control signal and the value stored by the register.

19. An integrated circuit device comprising:

means for sampling data from an external signal line in response to an internal clock signal;

means for storing a value that represents a timing offset to adjust the time at which the data is sampled;

means for generating the internal clock signal such that the internal clock signal maintains a controlled timing relationship with respect to an external clock signal, the generating means including means for phase mixing a set of reference clock signals such that the internal clock signal is phase offset in accordance with the value.

20. The device of claim 19, including means for generating the set of reference clock signals.

21. The device of claim 20, wherein

the phase mixing means comprises a first phase mixing means, the internal clock signal comprises a first internal clock signal, and the generating means further includes a second phase mixing means that generates a second internal clock signal, wherein both the first phase mixing means and the second phase mixing means are coupled the means for generating the set of reference clock signals;

the generating means further includes means for comparing a phase of the external clock with a phase of the second internal clock signal and for generating a phase adjustment value, wherein the second phase mixing means is configured to receive the phase adjustment value and to adjust the phase of the second internal signal in accordance with the phase adjustment value; and

the first phase mixing means is configured to generate the first internal clock signal in accordance with the phase adjustment value and the value that represents the timing offset.