Decomposing IC regions and embedding routes

• US 6,951,006 B1
• Filed: 08/14/2002
• Issued: 09/27/2005
• Est. Priority Date: 01/22/2002
• Status: Expired due to Fees

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Teig, Steven, Caldwell, Andrew
• Primary Examiner(s): Siek, Vuthe
• Application Number:
  US10/219,706
• Time in Patent Office: 1,140 Days
• Field of Search: 716/2, 716 7- 15
• US Class Current: 716/129
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

Some embodiments of the invention provide a method of identifying routes in a region of an integrated circuit (“IC”) design layout. The region contains at least one net with several routable elements. The method decomposes the IC design-layout region into a tessellated graph. The tessellated graph includes a plurality of edges. The method then specifies a route that connects the net'"'"'s routable elements by specifying a set of edges that the route intersects.

Claims

1. A method of identifying routes in a region of an integrated circuit (“

IC”

) design layout, the region containing at least one net with a plurality of routable elements, the method comprising;

a) decomposing the IC design-layout region into a tessellated graph, wherein the tessellated graph includes a plurality of edges and a plurality of nodes, each edge being between a pair of nodes; and

b) specifying a route that connects the net'"'"'s routable elements by specifying a set of edges that the route intersects, the specifying the set of edges comprising;

defining an associated set of edge intersections, each edge intersection representing the intersection of an edge and the route,

wherein the tessellated graph includes a plurality of faces, wherein the method further comprises specifying via locations within the faces, wherein specifying the route further comprises specifying a via location that the route uses.

2. The method of claim 1, wherein decomposing the region comprises triangulating the region into a plurality of triangular faces.

3. The method of claim 1, wherein the tessellated graph includes a plurality of faces, wherein the specified route uses a via that is defined within a face.

4. The method of claim 1, wherein specifying a via location comprises:

identifying at least two regions within at least two faces on two different layers of the tessellated graph;

identifying the intersection of the two regions;

determining whether the intersection of the two regions is sufficiently large for containing a via; and

specifying a via location if the identified intersection is sufficiently large.

5. The method of claim 4, wherein the method identifies and intersects the two regions and specifies the via location within the identified intersection before identifying the route for the net.

6. The method of claim 4, wherein the method identifies and intersects the two regions and specifies the via location within the identified intersection while defining the route that uses the via.

7. The method of claim 1, wherein the route for the net includes a set of paths, wherein identifying the route for the net comprises using an IDA* path search to identify each path of the route for the net.

8. The method of claim 1, wherein the route for the net includes a set of topological paths, wherein identifying the routes comprises identifying each path of the route for the net by using a best first search that expresses the cost of a path that reaches an item in the tessellated graph in terms of a function that is defined over the item.

15. The method of claim 1, wherein the layout has a coordinate system with at least two coordinate axes, wherein at least some of the edges are not parallel to either coordinate axis.

9. A computer readable medium comprising a computer program having executable code, the computer program for identifying routes in a region of an integrated circuit (“

IC”

) design layout, the region containing at least one net with a plurality of routable elements, the computer program comprising sets of instructions for;

a) decomposing the IC design-layout region into a tessellated graph, wherein the tessellated graph includes a plurality of edges and a plurality of nodes, each edge being between a pair of nodes;

a

b) specifying a route that connects the net'"'"'s routable elements by specifying a set of edges that the route intersects, the specifying the set of edges comprising;

defining an associated set of edge intersections, each edge intersection representing the intersection of an edge and the route,

wherein the tessellated graph includes a plurality of faces, wherein the computer program further comprises instructions for specifying via locations within the faces, wherein the instructions for specifying the route further comprises instructions for specifying a via location that the route uses.

10. The computer readable medium of claim 9, wherein the instructions for decomposing the region comprises instructions for triangulating the region into a plurality of triangular faces.

11. The computer readable medium of claim 9, wherein the tessellated graph includes a plurality of faces, wherein the specified route uses a via that is defined within a face.

12. The computer readable medium of claim 9, wherein the instructions for specifying a via location comprises instructions for:

identifying at least two regions within at least two faces on two different layers of the tessellated graph;

identifying the intersection of the two regions;

determining whether the intersection of the two regions is sufficiently large for containing a via; and

specifying a via location if the identified intersection is sufficiently large.

13. The computer readable medium of claim 12, wherein the computer program identifies and intersects the two regions and specifies the via location within the identified intersection before identifying the route for the net.

14. The computer readable medium of claim 12, wherein the computer program identifies and intersects the two regions and specifies the via location within the identified intersection while defining the route that uses the via location.

16. The computer readable medium of claim 9, wherein the layout has a coordinate system with at least two coordinate axes, wherein at least some of the edges are not parallel to either coordinate axis.