Dual-oxide transistors for the improvement of reliability and off-state leakage

• US 6,951,792 B1
• Filed: 03/11/2004
• Issued: 10/04/2005
• Est. Priority Date: 07/05/2001
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: McElheny, Peter John, Liu, Yowjuang Bill
• Primary Examiner(s): Lebentritt, Michael
• Assistant Examiner(s): LINDSAY JR, WALTER LEE
• Application Number:
  US10/800,221
• Time in Patent Office: 572 Days
• Field of Search: 438/286, 438/591, 438/594, 438/714, 438/770, 438/301, 438/303, 438/302
• US Class Current: 438/286
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: Y10S 438/981 Utilizing varying dielectric thickness

Abstract

The invention provides a transistor having low leakage currents and methods of fabricating the transistor on a semiconductor substrate. The transistor has a gate and a nonuniform gate oxide under the gate.

Claims

1. A method for fabricating a transistor on a semiconductor substrate, comprising the steps of:

forming a first oxide layer on the substrate;

forming a second oxide layer on the substrate; and

forming a gate over the substrate;

wherein the first oxide layer and the second oxide layer form a composite oxide layer under the gate, the composite oxide layer being thicker near at least one end of a width of the gate.

2. The method of claim 1 wherein the step of forming the first oxide layer further comprises:

forming an initial oxide layer that uniformly covers an active area of the transistor; and

etching away the initial oxide layer in most of the active area, leaving a portion of the initial oxide layer in a location over which a part the gate is formed.

3. The method of claim 2 wherein the step of etching away an area of the initial oxide layer to create the first oxide layer is performed using a low voltage mask that covers a portion of the active area near where an end of the gate is formed.

4. The method of claim 3 wherein the portion of the active area covered by the low voltage mask extends beyond sides of the gate.

5. The method of claim 1 further comprising forming lightly doped drain regions of the transistor by implanting dopants through the composite oxide layer, wherein the dopants are partially blocked or attenuated during the implant by the thicker composite oxide layer near an end of the gate.

6. The method of claim 1 further comprising forming spacers adjacent the gate.

7. The method of claim 1 further comprising forming source and drain regions of the transistor by implanting dopants through the composite oxide layer, wherein the dopants are partially blocked or attenuated during the implant by the thicker composite oxide layer near an end of the gate.

8. The method of claim 1 wherein the step of forming the first oxide layer comprises;

placing a mask over the substrate, the mask covering most of an active area of the transistor, leaving exposed to an oxidation ambient a portion of the active area in a location over which a part of the gate is formed; and

oxidizing the substrate in the oxidation ambient to form the first oxide layer.

9. The method of claim 1 wherein the step of forming the second oxide layer further comprises;

placing a mask over the substrate, the mask covering most of an active area of the transistor, leaving exposed to an oxidation ambient a portion of the active area in a location over which a part of the gate is formed; and

oxidizing the substrate in the oxidation ambient to form the second oxide layer.

10. A method for fabricating a transistor on a semiconductor substrate, comprising the steps of:

forming a first oxide layer on the substrate;

forming a second oxide layer on the substrate;

forming a gate over the substrate;

wherein the first oxide layer and the second oxide layer form a composite oxide layer under the gate, the composite oxide layer being thicker near at least one end of the gate; and

forming lightly doped drain regions in the substrate by implanting dopants through the composite oxide layer, wherein the dopants are partially blocked or attenuated during the implant by the thicker composite oxide layer near an end of the gate.

11. A method for fabricating a transistor on a semiconductor substrate, comprising the steps of:

forming a first oxide layer on the substrate;

forming a second oxide layer on the substrate; and

forming a gate over the substrate extending between first and second isolation regions;

wherein the first oxide layer and the second oxide layer form a composite oxide layer under the gate, the composite oxide layer being thicker near at least one of the first and second isolation regions.