Capacitor-built-in type printed wiring substrate, printed wiring substrate, and capacitor

• US 6,952,049 B1
• Filed: 03/29/2000
• Issued: 10/04/2005
• Est. Priority Date: 03/30/1999
• Status: Expired due to Term

• Current Assignee: NGK Spark PLUG Company Limited
• Original Assignee: NGK Spark PLUG Company Limited
• Inventors: Kodera, Eiji, Ogawa, Kouki
• Primary Examiner(s): Pham, Hoai
• Assistant Examiner(s): Ha, Nathan W.
• Application Number:
  US09/538,469
• Time in Patent Office: 2,015 Days
• Field of Search: 257/700, 257/701, 257702-707, 257/678
• US Class Current: 257/700
• CPC Class Codes: H01G 4/232 electrically connecting two or more layers of a stacked or rolled capacitor
• CPC Class Codes: H01G 4/236 leading through the housing, i.e. lead-through
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/16265 the item being a discrete passive component
• CPC Class Codes: H01L 2224/16268 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01068 Erbium [Er]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/19103 : interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/19106 : in a mirrored arrangement on two different side of a common die mounting substrate
• CPC Class Codes: H05K 1/0231 : Capacitors or dielectric substances
• CPC Class Codes: H05K 1/183 : Components mounted in and supported by recessed areas of the printed circuit board
• CPC Class Codes: H05K 2201/10515 : Stacked components
• CPC Class Codes: H05K 2201/1053 : Mounted components directly electrically connected to each other, i.e. not via the PCB
• CPC Class Codes: H05K 2201/10674 : Flip chip
• CPC Class Codes: H05K 2201/10734 : Ball grid array [BGA]; Bump grid array
• CPC Class Codes: H05K 2203/047 : Soldering with different solders, e.g. two different solders on two sides of the PCB
• CPC Class Codes: H05K 3/4602 : characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Abstract

A capacitor-built-in-type printed wiring substrate which can reliably eliminate noise and attain extremely low resistance and low inductance in connections between an IC chip and the capacitor, and a printed wiring substrate and capacitor for use in the same. A capacitor-built-in-type printed wiring substrate 100 on which an IC chip is mounted includes a capacitor-built-in-type printed wiring substrate 110 and an IC chip 101 mounted on the capacitor-built-in-type printed wiring substrate 110. A printed wiring substrate 120 includes a number of connection-to-IC substrate bumps 152 and a closed-bottomed capacitor accommodation cavity 121 formed therein. A capacitor 130 is disposed in the cavity 121 and includes a pair of electrode groups 133E and 133F and a number of connection-to-IC capacitor bumps 131 connected to either one of the paired electrode groups 133E and 133F. The connection-to-IC capacitor bumps 131 are flip-chip-bonded to corresponding connection-to-capacitor bumps 103 on the IC chip 101. The connection-to-IC substrate bumps 152 are flip-chip-bonded to corresponding connection-to-substrate bumps 104 on the IC chip 101.

Claims

1. A printed wiring substrate having a planar surface and a built-in capacitor having vertical sides on which an IC chip is mounted, said printed wiring substrate comprising a capacitor accommodation cavity selected from the group consisting of a closed-bottom cavity and a through hole cavity extending in the thickness direction of the printed wiring substrate and a capacitor disposed in said cavity, wherein the vertical sides of the capacitor and the printed wiring substrate are fixed together with an insulating resin filling a gap between the cavity and the capacitor, characterized in that:

the capacitor comprises;

a pair of electrodes or electrode groups; and

the capacitor comprises a plurality of capacitor terminals, wherein the respective capacitor terminals are electrically connected to one or the other of the paired electrodes or electrode groups;

the printed wiring substrate comprises a plurality of substrate terminals;

the IC chip comprises a plurality of connection-to-capacitor terminals and a plurality of connection-to-substrate terminals;

the plurality of capacitor terminals of the capacitor are respectively flip-chip-bonded directly to a plurality of connection-to-capacitor terminals of the IC chip; and

the plurality of substrate terminals of the printed wiring substrate are respectively flip-chip-bonded to a plurality of connection-to-substrate terminals of the IC chip.

2. The printed wiring substrate according to claim 1, characterized in that:

the printed wiring substrate comprises a core substrate made of resin and a capacitor accommodation cavity for accommodating the capacitor; and

the capacitor comprises a dielectric layer made of ceramic and electrodes arranged in alternating layers.

3. A printed wiring substrate having a planar surface and a built-in capacitor having vertical sides on which an IC-chip-carrying printed wiring substrate is mounted, said printed wiring substrate comprising a capacitor accommodation cavity selected from the group consisting of a closed-bottom cavity and a through hole cavity extending in the thickness direction of the printed wiring substrate and a capacitor disposed in said cavity, wherein the vertical sides of the capacitor and the printed wiring substrate are fixed together with an insulating resin filling a gap between the cavity and the capacitor, characterized in that:

the capacitor comprises;

a pair of electrodes or electrode groups; and

the capacitor comprises a plurality of capacitor terminals, wherein the respective capacitor terminals are electrically connected to one or the other of the paired electrodes or electrode groups;

the printed wiring substrate comprises a plurality of substrate terminals;

the IC chip-carrying printed wiring circuit comprises a plurality of connection-to-capacitor terminals and a plurality of connection-to-substrate terminals;

the plurality of capacitor terminals of the capacitor are respectively bonded in a connection-face-to-connection-face manner directly to a plurality of connection-to-capacitor terminals of the IC-chip-carrying printed wiring substrate; and

the plurality of substrate terminals of the printed wiring substrate are respectively bonded in a connection-face-to-connection-face manner to a plurality of connection-to-substrate terminals of the IC-chip-carrying printed wiring substrate.

4. The printed wiring substrate according to claim 3, wherein the IC-chip-carrying printed wiring substrate is a CSP adapted for mounting an IC chip.

5. The printed wiring substrate according to claim 4, characterized in that:

the printed wiring substrate comprises a core substrate made of resin and a capacitor accommodation cavity for accommodating the capacitor; and

the capacitor comprises a dielectric layer made of ceramic and electrodes arranged in alternating layers.

6. A printed wiring substrate having a planar surface and a built-in capacitor having vertical sides for mounting an IC chip or IC-chip-carrying printed wiring substrate having a plurality of connection-to-capacitor terminals and a plurality of connection-to-substrate terminals, said printed wiring substrate comprising a capacitor accommodation cavity selected from the group consisting of a closed-bottom cavity and a through hole cavity extending in the thickness direction of the printed wiring substrate and a capacitor disposed in said cavity, wherein the vertical sides of the capacitor and the printed wiring substrate are fixed together with an insulating resin filling a gap between the cavity and the capacitor, characterized in that:

the capacitor comprises;

a pair of electrodes or electrode groups; and

the capacitor comprises a plurality of capacitor terminals capable of being respectively flip-chip-bonded or bonded in a connection-face-to-connection-face manner to a plurality of connection-to-capacitor terminals of the IC chip or IC-chip-carrying printed wiring substrate, wherein the respective capacitor terminals are electrically connected to one or the other of the paired electrodes or electrode group; and

the printed wiring substrate comprises a plurality of substrate terminals capable of being respectively flip-chip-bonded or bonded in a connection-face-to-connection-face manner directly to a plurality of connection-to-substrate terminals of the IC chip or IC-chip-carrying printed wiring substrate.

7. The printed wiring substrate according to claim 6, wherein the capacitor and the printed wiring substrate are fixed together with an insulating resin.

8. The printed wiring substrate according to claim 6, characterized in that:

the capacitor comprises a first capacitor main-surface, on which the plurality of capacitor terminals are formed;

the printed wiring substrate comprises a first substrate main-surface, on which the plurality of substrate terminals are formed; and

the plurality of capacitor terminals and the plurality of substrate terminals are substantially coplanar.

9. The printed wiring substrate according to claim 6, characterized in that:

the printed wiring substrate comprises;

a capacitor accommodation cavity for accommodating the capacitor; and

a cavity periphery region located around the capacitor accommodation cavity; and

the plurality of substrate terminals are formed in the cavity periphery region.

10. The printed wiring substrate according to claim 6, characterized in that:

the printed wiring substrate comprises a capacitor accommodation cavity for accommodating the capacitor, said capacitor being disposed in the capacitor accommodation cavity; and

the capacitor accommodation cavity comprises a capacitor position restriction portion which abuts the capacitor disposed therein so as to restrict a position of the capacitor in a depth direction of the capacitor accommodation cavity.

11. The printed wiring substrate according to claim 6, characterized in that:

the printed wiring substrate assumes a substantially plate shape having a first substrate main-surface and a second substrate main-surface and comprises;

a closed-bottomed capacitor accommodation cavity which is sunk below the first substrate main-surface toward the second substrate main-surface and is adapted to accommodate the capacitor;

a plurality of second-surface substrate terminals formed on the second substrate main-surface; and

a plurality of connection lines extending from some of the plurality of second-surface substrate terminals to a bottom surface of the closed-bottomed capacitor accommodation cavity;

the capacitor is disposed in the closed-bottomed capacitor accommodation cavity and comprises;

a first capacitor main-surface;

a second capacitor main-surface substantially parallel to the first capacitor main-surface; and

a plurality of second-surface capacitor terminals formed on the second capacitor main-surface, wherein the respective second-surface capacitor terminals are electrically connected to one or the other of the paired electrodes or electrode groups;

the plurality of substrate terminals are formed on the first substrate main-surface;

the plurality of capacitor terminals are formed on the first capacitor main-surface; and

the plurality of second-surface capacitor terminals are connected to corresponding connection lines which extend to the bottom surface of the closed-bottomed capacitor accommodation cavity.

12. The wiring substrate according to claim 6, characterized in that:

the printed wiring substrate assumes a substantially plate shape having a first substrate main-surface and a second substrate main-surface and comprises;

a through capacitor accommodation cavity which extends through the printed wiring substrate between the first substrate main-surface and the second substrate main-surface and is adapted to accommodate the capacitor; and

a plurality of second-surface substrate terminals formed on the second substrate main-surface;

the capacitor is disposed in the through capacitor accommodation cavity and comprises;

a first capacitor main-surface;

a second capacitor main-surface substantially parallel to the first capacitor main-surface; and

a plurality of second-surface capacitor terminals formed on the second capacitor main-surface, wherein the respective second-surface capacitor terminals are electrically connected to one or the other of the paired electrodes or electrode groups;

the plurality of substrate terminals are formed on the first substrate main-surface; and

the plurality of capacitor terminals are formed on the first capacitor main-surface.

13. The printed wiring substrate according to claim 11, wherein the plurality of second-surface capacitor terminals are disposed at intervals greater than those of the plurality of capacitor terminals.

14. The printed wiring substrate according to claim 12, wherein the plurality of second-surface capacitor terminals are disposed at intervals greater than those of the plurality of capacitor terminals.

15. The printed wiring substrate according to claim 6, wherein the printed wiring substrate serves as an interposer between the IC-chip-carrying printed wiring substrate and another printed wiring substrate.

16. The printed wiring substrate according to claim 6, characterized in that:

the printed wiring substrate comprises a core substrate made of resin and a capacitor accommodation cavity for accommodating the capacitor; and

the capacitor comprises a dielectric layer made of ceramic and electrodes arranged in alternating layers.