Phase locked loop circuit with self adjusted tuning hiep the pham
First Claim
1. A phase-locked loop (PLL) circuit, comprising:
- a voltage-controlled oscillator (VCO) having a first input to receive a control voltage, one or more second inputs to receive one or more tuning range signals, and an output to provide an oscillation output signal;
a phase detector having inputs to receive the oscillation output signal and a reference signal, and having an output;
a charge pump having an input coupled to the output of the phase detector and having an output to generate the control voltage;
a loop filter having an input to receive the control voltage and having a control terminal; and
a control circuit having inputs to receive the control voltage, a high reference voltage, a low reference voltage, and one or more mode signals, and having a first output connected to the control terminal of the loop filter and second outputs to generate the tuning range signals, wherein the control circuit is configured to automatically generate the tuning range signals when the mode signals are set to a first state.
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Accused Products
Abstract
A phase-locked loop (PLL) circuit includes a voltage-controlled oscillator (VCO) having a first input to receive a control voltage, one or more second inputs to receive one or more tuning range control signals, and an output to provide an oscillation output signal, a phase detector having inputs to receive the oscillation output signal and a reference signal, a charge pump having an input coupled to the output of the phase detector and having an output to generate the control voltage, a loop filter having an input to receive the control voltage and having a control terminal, and a controller having inputs to receive the control voltage, a high reference voltage, a low reference voltage, and one or more mode signals, and having a first output connected to the control terminal of the loop filter and second outputs to generate the tuning range signals.
69 Citations
34 Claims
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1. A phase-locked loop (PLL) circuit, comprising:
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a voltage-controlled oscillator (VCO) having a first input to receive a control voltage, one or more second inputs to receive one or more tuning range signals, and an output to provide an oscillation output signal;
a phase detector having inputs to receive the oscillation output signal and a reference signal, and having an output;
a charge pump having an input coupled to the output of the phase detector and having an output to generate the control voltage;
a loop filter having an input to receive the control voltage and having a control terminal; and
a control circuit having inputs to receive the control voltage, a high reference voltage, a low reference voltage, and one or more mode signals, and having a first output connected to the control terminal of the loop filter and second outputs to generate the tuning range signals, wherein the control circuit is configured to automatically generate the tuning range signals when the mode signals are set to a first state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A phase-locked loop (PLL) circuit, comprising:
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a voltage-controlled oscillator (VCO) having a first input to receive a control voltage, a second input to receive a tuning range signal that configures the VCO to one of a plurality of adjacent tuning ranges, and an output to provide an oscillation output signal;
a phase detector having inputs to receive the oscillation output signal and a reference signal, and having an output;
a charge pump and loop filter circuit having an input coupled to the output of the phase detector, an output to generate the control voltage, and a control terminal to receive a reset signal; and
a control circuit for automatically generating the tuning range signal in response to a comparison between the control voltage and a plurality of reference voltages when a mode signal is set to a first state. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28, 29)
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30. A method of operating a phase-locked loop (PLL) circuit having a plurality of substantially adjacent frequency tuning ranges, comprising:
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configuring the circuit to initially operate in a selected frequency tuning range;
generating an oscillation output signal;
comparing the oscillation output signal with a reference signal to generate a control voltage;
comparing the control voltage to first and second reference voltages to generate a compare signal, wherein the first reference voltage is less than the second reference voltage; and
selectively changing the frequency tuning range in response to the compare signal, wherein the selectively changing further comprises;
selecting a lower frequency tuning range if the control voltage is less than the first reference voltage;
selecting a higher frequency tuning range if the control voltage is greater than the second reference voltage; and
locking the selected frequency tuning range if the control voltage is between the first and second reference voltages. - View Dependent Claims (31, 32, 33, 34)
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Specification