Active matrix device and display

• US 6,952,244 B2
• Filed: 02/20/2002
• Issued: 10/04/2005
• Est. Priority Date: 02/27/2001
• Status: Expired due to Fees

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Dachs, Catherine Rosinda Marie Armida, Brownlow, Michael James, Cairns, Graham Andrew, Kaise, Yasuyoshi
• Primary Examiner(s): Nguyen, Dung T.
• Assistant Examiner(s): DI GRAZIO, JEANNE A
• Application Number:
  US10/081,917
• Publication Number:
  US 20020154253A1
• Time in Patent Office: 1,322 Days
• Field of Search: 349/43, 257/59
• US Class Current: 349/43
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136245 having complementary transistors
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence

Abstract

An active matrix devise comprises an array of picture elements. Each picture element has an image element, such as an LCD cell (11) connected to a first storage capacitor 12 and arranged to be connected to a data line 4 by an thin film transistor 10 when activated by a scan signal on a scan line 6. A second storage capacitor 21 can be connected across the first capacitor 12 by means of another thin film transistor 20 when desired so as to increase the storage capacitance at the pixel.

Claims

1. An active matrix device comprising an array of picture elements, each of which comprises an image element, a first charge storage element connected to the image element, and a first semiconductor switch for connecting a data line to the first charge storage element and the image element, characterised in that each picture element comprises a second charge storage element and a second semiconductor switch switchable independently of the first switch to connect the second charge storage element to the first charge storage element and the image element so as to increase the charge storage capacity.

2. A device as claimed in claim 1, characterised in that each image element is a light modulating element.

3. A device as claimed in claim 2, characterised in that each image element is transmissive.

4. A device as claimed in claim 2, characterised in that each image element is reflective.

5. A device as claimed in claim 2, characterised in that each image element is a liquid crystal element.

6. A device as claimed in claim 1, characterised in that each image element is a light emitting element.

7. A device as claimed in claim 1, characterised in that each of the first and second switches is a thin film transistor.

8. A device as claimed in claim 1, characterised in that the charge storage capacity of the second charge storage element is greater than that of the first charge storage element.

9. A device as claimed in claim 1, characterised in that, for each picture element, the second charge storage element and the second switch are connected in series and the series connection of the second charge storage element and the second switch is in parallel with the first charge storage element.

10. A device as claimed in claim 1, characterised in that the picture elements are arranged as rows and columns with the picture elements of each column being connected to a respective data line and the picture elements of each row being connected to a respective scan line.

11. A device as claimed in claim 10, characterised in that the second switches of each row of picture elements have control terminals connected to a respective control line.

12. A device as claimed in claim 11, characterised in that the control lines are connected together.

13. A device as claimed in claim 1, characterised in that, for each picture element, the second switch has a control terminal connected to first terminals of the first and second charge storage elements.

14. A device as claimed in claim 10, characterised in that the first and second charge storage elements of each row of picture elements have first terminals connected to a respective common line.

15. A device as claimed in claim 10, characterised in that the first and second charge storage elements of each adjacent pair of rows of picture elements have first terminals connected to a respective common line.

16. A device as claimed in claim 10, characterised in that the first and second charge storage elements of each row of picture elements have first terminals connected to the scan line of an adjacent row.

17. A device as claimed in claim 1, characterised in that the first and second charge storage elements of each picture element comprise first and second capacitors, respectively.

18. A device as claimed in claim 17, characterised in that the first and second capacitors of each picture element have a common plate.

19. A device as claimed in claim 18, characterised in that the common plate comprises a part of a gate metal interconnect layer (GL).

20. A device as claimed in claim 19, characterised in that the first capacitor of each picture element has a further plate comprising part of a source metal interconnect layer (SL).

21. A device as claimed in claim 19, characterised in that the second capacitor of each picture element has a further plate comprising part of a heavily doped silicon layer.

22. A device as claimed in claim 17, characterised in that the second capacitor of each picture element has a dielectric comprising gate oxide.

23. A device as claimed in claim 22, characterised in that the second capacitor of each picture element comprises a metal oxide silicon capacitor.

24. A device as claimed in claim 23, characterised in that the metal oxide silicon capacitor forms the second switch and has source and drain terminals connected to the first switch and the image element.

25. A device as claimed in claim 23, characterised in that the first capacitor of each picture element comprises the gate/source overlap capacitance and the gate/drain overlap capacitance of the metal oxide silicon capacitor.

26. A device as claimed in claim 25, characterised in that the metal oxide silicon capacitor (35) has a lightly doped drain below the gate electrode.

27. A display characterised by comprising a device as claimed in claim 1.