Reducing the effects of noise in non-volatile memories through multiple reads

• US 6,952,365 B2
• Filed: 03/12/2004
• Issued: 10/04/2005
• Est. Priority Date: 01/18/2002
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Gonzalez, Carlos J., Guterman, Daniel C.
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US10/799,416
• Publication Number:
  US 20040170058A1
• Time in Patent Office: 571 Days
• Field of Search: 365/185.03, 365/185.21, 365/185.18
• US Class Current: 365/185.03
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2013/0057 Read done in two steps, e.g. wherein the cell is read twice and one of the two read values serving as a reference value
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/106 Data output latches

Abstract

Storage elements are read multiple times and the results are accumulated and averaged for each storage element to reduce the effects of noise or other transients in the storage elements and associated circuits that may adversely affect the quality of the read. Several techniques may be employed, including: A full read and transfer of the data from the storage device to the controller device for each iteration, with averaging performed by the controller; a full read of the data for each iteration, with the averaging performed by the storage device, and no transfer to the controller until the final results are obtained; one full read followed by a number of faster re-reads exploiting the already established state information to avoid a full read, followed by an intelligent algorithm to guide the state at which the storage element is sensed. These techniques may be used as the normal mode of operation, or invoked upon exception condition, depending on the system characteristics. A similar form of signal averaging may be employed during the verify phase of programming. An embodiment of this technique would use a peak-detection scheme. In this scenario, several verify checks are performed at the state prior to deciding if the storage element has reached the target state. If some predetermined portion of the verifies fail, the storage element receives additional programming. These techniques allow the system to store more states per storage element in the presence of various sources of noise.

Claims

1. A method of sensing the data content of a non-volatile memory, comprising:

biasing a multi-state storage element of the non-volatile memory according to a set of operating parameters and target criteria;

determining to a first resolution the value of a parameter indicative of the state of said storage element a plurality of times with the storage element biased according to said set of operating parameters and target criteria;

individually storing said plurality of parameter values determined to the first resolution; and

determining the multi-state data content of said storage element to a second resolution less than said first resolution by forming a composite of said plurality of values of said parameter individually stored at the first resolution.

2. A method according to claim 1, wherein the storage element is a charge storing device.

3. A method according to claim 2, wherein the step of determining the value of a parameter is performed to yield a digital value.

4. A method according to claim 2, wherein the parameter is one of a current;

a voltage;

a time;

a frequency;

a magnetic property; and

an optical property.

5. A method according to claim 2, wherein the forming a composite comprises one of the following:

adding the plurality of parameter values to form a sum; and

dividing the sum by the number of parameter values added;

forming a mean of the plurality of parameter values;

forming a weighted mean of the plurality of parameter values;

a peak detection scheme; and

omitting outlying values of the plurality of parameter values.

6. A method according to claim 5, wherein the forming a composite comprises adding the plurality of parameter values to form a sum;

and dividing the sum by the number of parameter values added.

7. A method according to claim 2, wherein the non-volatile memory comprises a memory unit containing a plurality of storage elements including said storage element and a controller, and wherein the composite is formed by the controller.

8. A method according to claim 7, wherein the values of the parameter indicative of the state of the storage element are individually stored on one of the controller or the memory prior to the forming a composite.

9. A method according to claim 1, wherein said storage element is one of a plurality of storage elements read concurrently.

10. A method according to claim 1, wherein the non-volatile memory comprises a memory unit containing a plurality of storage elements including said storage element and a controller, and wherein the values of the parameter indicative of the state of said storage element are individually stored on the memory unit prior to the forming a composite and wherein the composite is formed by the memory unit.

11. A method according to claim 1, performed as part of the verify phase of a programming operation.

12. A method according to claim 1, wherein the determining the value of a parameter indicative of the state of the storage element comprises:

determining a base value for the parameter; and

determining variation from the vase value a plurality of times.

13. A non-volatile memory comprising:

an array of multi-state storage elements;

read circuitry coupled to the array to provide a parameter associated with the state of a cell contained therein;

a sense amplifier coupled to the read circuitry to determine the value of the parameter to a first resolution; and

averaging circuitry coupled to the sense amplifier for individually storing multiple independently determined values of the parameter supplied from the sense amplifier at the first resolution and forming a composite multi-state data value of a second resolution less than the first resolution for the single cell formed from said multiple independently determined values of the parameter supplied from the sense amplifier at the first resolution.

14. A memory according to claim 13, wherein the parameter is one of a current level;

a voltage level;

a time;

a frequency;

a magnetic property; and

an optical property.

15. A memory according to claim 13, wherein the averaging circuitry comprises an adder to produce a sum of the multiple independently determined values and a division circuit for dividing the sum by the number of independently determined values added to produce the sum.

16. A memory according to claim 13, wherein the memory comprises a storage section that includes the array, read circuitry, and sense amplifier and a controller section that includes the averaging circuitry.

17. A memory according to claim 16, wherein the controller section includes a plurality of registers wherein the multiple independently determined values of the parameter supplied from the sense amplifier are stored prior to being supplied to the averaging circuitry.

18. A memory according to claim 13, wherein the memory comprises a controller section and a storage section, the storage section including the array, read circuitry, sense amplifier and the averaging circuitry.

19. A memory according to claim 18, wherein the controller section includes a plurality of registers wherein the multiple independently determined values of the parameter supplied from the sense amplifier are stored prior to being supplied to the averaging circuitry.

20. A memory according to claim 13 including programming circuitry coupled to the array for changing the state of the storage elements contained therein and coupled to the averaging circuitry for receiving the composite value, wherein the composite value is used during the verify phase of a programming process.

21. A non-volatile memory-comprising an array of storage elements, biasing circuitry whereby selected storage elements can be biased, and read circuitry to provide the data content of the selected elements when biased by the biasing circuitry, wherein the read circuitry senses the selected storage elements in a first mode, wherein the selected storage elements are sensed once for each of one or more first sets of bias conditions, subsequently senses the selected storage elements in a second mode, wherein the selected storage elements are sensed a plurality of times for each of one or more second sets of bias conditions which differ from the first sets of bias conditions, and determines the data content of the selected storage elements from a combination of the sensing in the first mode and the sensing in the second mode.