Method and apparatus for verifying the integrity of control module operation
First Claim
1. A method for verifying the integrity of operation of a control module having a digital signal processing unit, the method comprising steps of:
- conveying a seed value to the digital signal processing unit;
incrementing a stored state value;
executing, by the digital signal processing unit, a set of verification instructions based on the seed value to produce a verification set output value;
receiving, from the digital signal processing unit, the verification set output value;
further incrementing the stored state value to produce a twice incremented second state value;
comparing the verification set output value to an expected result to produce a comparison; and
determining whether an error has occurred based on the comparison.
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Accused Products
Abstract
A control module (100) includes a first signal processing unit (102) that is coupled to a second signal processing unit (114) by a control bus (130), an address bus (131) and a data bus (132). The control module conveys seed value addresses (108) and expected result addresses (110) over the address bus, seed values (118) and verification set output values (107) over the data bus, and compares each verification set output value to an expected result (120), thereby allowing the control module to determine whether the first signal processing unit, the control bus, the address bus, and the data bus are collectively functioning correctly. By properly selecting the seed value addresses, expected result addresses, seed values, and expected results (and correspondingly, verification set output values), proper operation of each line of the address bus and control bus may be individually verified.
65 Citations
20 Claims
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1. A method for verifying the integrity of operation of a control module having a digital signal processing unit, the method comprising steps of:
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conveying a seed value to the digital signal processing unit;
incrementing a stored state value;
executing, by the digital signal processing unit, a set of verification instructions based on the seed value to produce a verification set output value;
receiving, from the digital signal processing unit, the verification set output value;
further incrementing the stored state value to produce a twice incremented second state value;
comparing the verification set output value to an expected result to produce a comparison; and
determining whether an error has occurred based on the comparison. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for verifying the integrity of operation of a control module having a first digital signal processing unit coupled to second digital signal processing unit, wherein the first digital signal processing unit stores a set of verification instructions, wherein the first digital signal processing unit stores a plurality of seed value addresses and the second digital signal processing unit stores a plurality of seed values and a plurality of expected results, the method comprising steps of:
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(a) conveying, by the second digital signal processing unit to the first digital signal processing unit, a seed value of the plurality of seed values, wherein this step includes the substeps of;
conveying, by the first digital signal processing unit to the second digital signal processing unit, a seed value address of the plurality of seed value addresses, receiving, by the second digital signal processing unit, the seed value address, retrieving, by the second digital signal processing unit, a seed value, and conveying, by the second digital signal processing unit, the retrieved seed value;
(b) executing, by the first digital signal processing unit, the set of verification instructions based on the seed value to produce a verification set output value;
(c) conveying, by the first digital signal processing unit to the second digital signal processing unit, the verification set output value;
(d) comparing, by the second digital signal processing unit, the verification set output value to a corresponding expected result of the plurality of expected results to produce a comparison;
(e) determining whether an error has occurred based on one or more of the comparison of the received verification set output value to a corresponding expected result and the received seed value address;
(f) determining whether a predetermined number of iterations of steps (b) through (e) have been completed; and
(g) when fewer than the predetermined number of iterations have been completed, conveying a succeeding seed value of the plurality of seed values to the first digital signal processing unit and repeating steps (b) through (f). - View Dependent Claims (9, 10, 11, 12, 13)
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14. A control module that self-verifies the integrity of the control module'"'"'s operations, the control module comprising:
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a first digital signal processing unit that receives a seed value from a second digital signal processing unit, executes a set of verification instructions based on the seed value to produce a verification set output value, and conveys the verification set output value to the second digital signal processing unit; and
a second digital signal processing unit coupled to the first digital signal processing unit that stores the seed value and an expected result, retrieves the seed value based on a received seed value address received from the first digital signal processing unit, conveys the seed value to the first digital signal processing unit, receives the verification set output value from the first digital signal processing unit, compares the received verification set output value to the expected result to produce a comparison, and determines whether an error has occurred based on the comparison. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification