Electric device, matrix device, electro-optical display device and semiconductor memory having thin-film transistors

• US 6,953,713 B2
• Filed: 07/30/2001
• Issued: 10/11/2005
• Est. Priority Date: 05/29/1992
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Takemura, Yasuhiko, Yamazaki, Shunpei
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): Pham, Thanh V
• Application Number:
  US09/916,484
• Publication Number:
  US 20020000554A1
• Time in Patent Office: 1,534 Days
• Field of Search: 438/155, 438/164, 438/129, 438/599, 438/FOR.201, 438/FOR.218, 257/919
• US Class Current: 438/129
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/136245 having complementary transistors
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/78666 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 12/05 Making the transistor

Abstract

A circuit adapted to dynamically activate an electro-optical display device is constructed from a thin-film gate-insulated semiconductor device. This device comprises PMOS TFTs producing only a small amount of leakage current. Besides the dynamic circuit, a CMOS circuit comprising both NMOS and PMOS thin-film transistors is constructed to drive the dynamic circuit.

Claims

1. A method of manufacturing a semiconductor device:

the semiconductor device comprising;

at least two p-channel thin film transistors in a pixel portion,

each of the two p-channel thin film transistors in the pixel portion fabricated through the method comprising;

forming a semiconductor island over a substrate;

forming a gate electrode adjacent to the semiconductor island with a gate insulating film therebetween;

forming a source region, a drain region and a channel region formed between the source and drain regions,

wherein the two p-channel thin film transistors are connected in series,

wherein an off current from each of the p-channel thin film transistors is less than 10<sup>−

12</sup> A where a voltage of the drain region is 1V, and

wherein a pixel electrode is connected to a data line without any n-channel thin film transistor connected therebetween.

2. A method according to claim 1, further comprising:

forming a blocking film between the substrate and the semiconductor island,

wherein the substrate is a glass substrate;

wherein the blocking film includes,

a silicon nitride film with a thickness in a range of 5-200 nm formed on the glass substrate, and

a silicon oxide film with a thickness in a range of 20-1000 nm formed on the silicon nitride film.

3. A method according to claim 1, further comprising:

forming an interlayer insulating film including boro-phosphosilicate glass over the two p-channel thin film transistors.

4. A method according to claim 1, wherein the semiconductor island is a crystalline semiconductor island.

5. A method according to claim 1, wherein each of the source and drain regions comprises boron.

6. A method of manufacturing a display device, said display device comprising:

a pixel portion and a driving circuit portion;

at least two p-channel thin film transistors being formed in the pixel portion;

each of the two p-channel thin film transistors fabricated through the method comprising;

forming a semiconductor island over a substrate;

forming a gate electrode adjacent to the semiconductor island with a gate insulating film therebetween;

forming a source region, a drain region and a channel region formed between the source and drain regions,

wherein the two p-channel thin film transistors are connected in series,

wherein an off current from each of the p-channel thin film transistors is less than 10<sup>−

12</sup> A where a voltage of the drain region is 1V, and

wherein a pixel electrode is connected to a data line without any n-channel thin film transistor connected therebetween.

7. A method according to claim 6 further comprising:

forming a blocking film between the substrate and the semiconductor island,

wherein the substrate is a glass substrate;

wherein the blocking film includes,

a silicon nitride film with a thickness in a range of 5-200 nm formed on the glass substrate, and

a silicon oxide film with a thickness in a range of 20-1000 nm formed on the silicon nitride film.

8. A method according to claim 6, further comprising:

forming an interlayer insulating film including boro-phosphosilicate glass over the two p-channel thin film transistors.

9. A method according to claim 6, wherein the semiconductor island is a crystalline semiconductor island.

10. A device according to claim 6, wherein each of the source and drain regions comprises boron.

11. A method of manufacturing a semiconductor device, said semiconductor device comprising:

at least a first p-channel thin film transistor and a second p-channel thin film transistor in a pixel portion;

a transmission gate including a CMOS circuit, said CMOS circuit including at least an n-channel thin film transistor and a third p-channel thin film transistor;

each of the first, second and third p-channel thin film transistors fabricated through the method comprising;

forming a semiconductor island over a substrate;

forming a gate electrode adjacent to the semiconductor island with a gate insulating film therebetween;

forming a source region, a drain region and a channel region formed between the source and drain regions,

wherein the first and second p-channel thin film transistors are connected in series,

wherein an off current from each of the first, second and third p-channel thin film transistors is less than 10<sup>−

12</sup> A where a voltage of the drain region is 1V, and

wherein a pixel electrode is connected to a data line without any n-channel thin film transistor connected therebetween.

12. A method according to claim 11 further comprising:

forming a blocking film between the substrate and the semiconductor island,

wherein the substrate is a glass substrate,

wherein the blocking film includes,

a silicon nitride film with a thickness in a range of 5-200 nm formed on the glass substrate, and

a silicon oxide film with a thickness in a range of 20-1000 nm formed on the silicon nitride film.

13. A method according to claim 11 further comprising:

forming an interlayer insulating film including boro-phosphosilicate glass over the first, second and third p-channel thin film transistors and the n-channel thin film transistor.

14. A method according to claim 11, wherein the semiconductor island is a crystalline semiconductor island.

15. A method according to claim 11, wherein each of the source and drain regions of each of the first, second and third p-channel thin film transistors comprises boron.

16. A method according to claim 11, wherein each of the second source and drain regions of the n-channel thin film transistor comprises phosphorus.

17. A method of manufacturing a semiconductor device comprising:

the semiconductor device comprising at least two p-channel thin film transistors in a pixel portion,

each of the two p-channel thin film transistors fabricated through the method comprising;

forming an amorphous semiconductor film on an insulating surface over a substrate;

crystallizing the amorphous semiconductor film to form a crystalline semiconductor film;

patterning the crystalline semiconductor film to form a crystalline semiconductor island;

forming a gate electrode adjacent to the crystalline semiconductor island with a gate insulating film therebetween;

introducing a p-type impurity to form a source region, a drain region and a channel region formed between the source and drain regions,

wherein the two p-channel thin film transistors are connected in series,

wherein an off current from each of the p-channel thin film transistors is less than 10<sup>−

12</sup> A where a voltage of the drain region is 1V, and

wherein a pixel electrode is connected to a data line without any n-channel thin film transistor connected therebetween.

18. A method according to claim 17, further comprising:

forming a blocking film between the substrate and the crystalline semiconductor island,

wherein the substrate is a glass substrate;

wherein the blocking film includes,

a silicon nitride film with a thickness in a range of 5-200 nm formed on the glass substrate, and

a silicon oxide film with a thickness in a range of 20-1000 nm formed on the silicon nitride film.

19. A method according to claim 17, further comprising:

forming an interlayer insulating film including boro-phosphosilicate glass over the two p-channel thin film transistors.

20. A method according to claim 17, wherein each of the source and drain regions comprises boron.

21. A method according to claim 17, wherein the amorphous semiconductor film is crystallized by thermally annealing.

22. A method of manufacturing a semiconductor device comprising:

the semiconductor device comprising at least two p-channel thin film transistors in a pixel portion,

each of the two p-channel thin film transistors fabricated through the method comprising;

forming an amorphous semiconductor film on an insulating surface over a substrate;

annealing the amorphous semiconductor film with a laser light to crystallize the amorphous semiconductor film;

patterning the crystallized semiconductor film to form a crystalline semiconductor island;

forming a gate electrode adjacent to the crystalline semiconductor island with a gate insulating film therebetween;

introducing a p-type impurity to form a source region, a drain region and a channel region formed between the source and drain regions,

wherein the two p-channel thin film transistors are connected in series,

wherein an off current from each of the p-channel thin film transistors is less than 10<sup>−

12</sup> A where a voltage of the drain region is 1V, and

wherein a pixel electrode is connected to a data line without any n-channel thin film transistor connected therebetween.

23. A method according to claim 22, further comprising:

forming a blocking film between the substrate and the crystalline semiconductor island,

wherein the substrate is a glass substrate;

wherein the blocking film includes,

a silicon nitride film with a thickness in a range of 5-200 nm formed on the glass substrate, and

a silicon oxide film with a thickness in a range of 20-1000 nm formed on the silicon nitride film.

24. A method according to claim 22, further comprising:

forming an interlayer insulating film including boro-phosphosilicate glass over the two p-channel thin film transistors.

25. A method according to claim 22, wherein each of the source and drain regions comprises boron.

26. A method of manufacturing a semiconductor device comprising:

the semiconductor device comprising a plurality of p-channel thin film transistors in a pixel portion,

each of the plurality of the p-channel thin film transistors fabricated through the method comprising;

forming a semiconductor island over a substrate;

forming a gate electrode adjacent to the semiconductor island with a gate insulating film therebetween;

forming a source region, a drain region and a channel region formed between the source and drain regions,

wherein the plurality of p-channel thin film transistors are connected in series,

wherein an off current from each of plurality of the p-channel thin film transistors is less than 10<sup>−

12</sup> A where a voltage of the drain region is 1V, and

wherein a pixel electrode is connected to a data line without any n-channel thin film transistor connected therebetween.

27. A method according to claim 26, further comprising:

forming a blocking film between the substrate and the semiconductor island,

wherein the substrate is a glass substrate;

wherein the blocking film includes,

a silicon nitride film with a thickness in a range of 5-200 nm formed on the glass substrate, and

a silicon oxide film with a thickness in a range of 20-1000 nm formed on the silicon nitride film.

28. A method according to claim 26, further comprising:

forming an interlayer insulating film including boro-phosphosilicate glass over the two p-channel thin film transistors.

29. A method according to claim 26, wherein the semiconductor island is a crystalline semiconductor island.

30. A method according to claim 26, wherein each of the source and drain regions comprises boron.

31. A method according to claim 26, wherein the semiconductor device includes at least three p-channel thin film transistors connected in series.

32. A method of manufacturing a display device,

said display device comprising:

a pixel portion;

a drive circuit portion;

at least a first p-channel thin film transistor and a second p-channel thin film transistor in the pixel portion;

a transmission gate including a CMOS circuit in the drive circuit portion, said CMOS circuit including at least an n-channel thin film transistor and a third p-channel thin film transistor;

each of the first, second and third p-channel thin film transistors fabricated through the method comprising;

forming a semiconductor island over a substrate;

forming a gate electrode adjacent to the semiconductor island with a gate insulating film therebetween;

forming a source region, a drain region and a channel region formed between the source and drain regions,

wherein the first and second p-channel thin film transistors are connected in series,

wherein an off current from each of the first, second and third p-channel thin film transistors is less than 10<sup>−

12</sup> A where a voltage of the drain region is 1V,

wherein only p-channel thin film transistors connected in series are used as a switching element in the pixel portion, and

wherein the pixel portion does not include any n-channel thin film transistor.

33. A method according to claim 32 further comprising:

forming an interlayer insulating film including boro-phosphosilicate glass over the first, second and third p-channel thin film transistors and the n-channel thin film transistor.

34. A method according to claim 32, wherein the semiconductor island is a crystalline semiconductor island.

35. A method according to claim 32, wherein each of the source and drain regions of each of the first, second and third p-channel thin film transistors comprises boron.

36. A method according to claim 32, wherein each of the second source and drain regions of the n-channel thin film transistor comprises phosphorus.