Semiconductor device having borderless logic array and flexible I/O

• US 6,953,956 B2
• Filed: 12/18/2002
• Issued: 10/11/2005
• Est. Priority Date: 12/18/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: eASIC Corporation (Intel Corporation)
• Inventors: Or-Bach, Zvi, Cooke, Laurance
• Primary Examiner(s): QUACH, TUAN N
• Application Number:
  US10/321,669
• Publication Number:
  US 20040119098A1
• Time in Patent Office: 1,028 Days
• Field of Search: 257/202, 257/203, 257/620, 257/734, 257/773, 257/786
• US Class Current: 257/203
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A novel method is presented to provide ASICs with drastically reduced NRE and with volume flexibility. The invention includes a method of fabricating an integrated circuit, including the steps of: providing a semiconductor substrate, forming a borderless logic array including a plurality of Area I/Os and also including the step of forming redistribution layer for redistribution at least some of the Area I/Os for the purpose of the device packaging. The fabrication may utilize Direct Write e-Beam for customization. The customization step may include fabricating various types of devices at different volume from the same wafer.

Claims

1. A semiconductor device comprising:

a borderless logic array;

area I/Os; and

a redistribution layer for redistributing at least some of said area I/Os.

2. A semiconductor device according to claim 1 and wherein at least one pad used to connect said semiconductor device to other devices overlays at least a portion of the logic array or a portion of the area I/Os.

3. A semiconductor device according to claim 1 and also comprising:

a borderless memory array.

4. A semiconductor device according to claim 1 and wherein said logic array comprises:

a module array.

5. A semiconductor device according to claim 1, further comprising interconnections within the logic array, wherein said logic array interconnections comprise metal layers and via layers, and wherein at least one of said metal layers comprises at least one substantially repeating pattern for a portion used for said interconnections.

6. A semiconductor device according to claim 5 and wherein at least two of said metal layers comprise substantially repeating patterns for portions used for said interconnections.

7. A semiconductor device according to claim 5 and wherein at least three of said metal layers comprise substantially repeating patterns for portions used for said interconnections.

8. A semiconductor device according to claim 1 and wherein said area I/Os are positioned in a non-surrounding fashion with respect to said logic array.

9. A semiconductor device according to claim 1 and wherein said logic array comprises a repeating module, and wherein said area I/Os are positioned in a non-surrounding fashion with respect to at least one of said repeating module.

10. A semiconductor device according to claim 1, wherein said logic array comprises a repeating core, and wherein at least one of said area I/Os is a configurable I/O.

11. A semiconductor device according to claim 1 and wherein said borderless logic array is formed by a process that includes a step of positioning said area I/Os in a non-surrounding fashion with respect to said logic array.

12. A semiconductor device according to claim 1 and wherein said logic array comprises a repeating core, and wherein said borderless logic array is formed by a process that includes a step of positioning said area I/Os in a non-surrounding fashion with respect to said logic array.

13. A semiconductor device according to claim 1, wherein said logic array comprises a repeating core, and wherein said borderless logic array is formed by a process that includes a step of positioning said area I/Os within said core, and wherein at least one of said area I/Os is configurable I/O.

14. A semiconductor device as in claim 1, wherein at least one of said area I/Os comprises a configurable I/O.

15. A semiconductor device as in claim 14, wherein said configurable I/O comprises multiple copies of input, output, and pre-output cells, and wherein the semiconductor device further comprises connections between at least one of said input, output, and pre-output cells and area I/O pads to construct an area I/O.