High voltage withstanding semiconductor device

• US 6,953,968 B2
• Filed: 01/19/2001
• Issued: 10/11/2005
• Est. Priority Date: 01/19/2001
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Nakamura, Hideki, Nakamura, Katsumi, Kusunoki, Shigeru
• Primary Examiner(s): Tran, Minhloan
• Assistant Examiner(s): TRAN, TAN N
• Application Number:
  US10/221,273
• Publication Number:
  US 20030042537A1
• Time in Patent Office: 1,726 Days
• Field of Search: 257/328, 257/329, 257/330, 257/331, 257/301, 257/302, 257/332, 257/338, 257/310
• US Class Current: 257/328
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

A semiconductor device of the present invention has an insulating gate type field effect transistor portion having an n-type emitter region (3) and an n⁻ silicon substrate (1), which are opposed to each other sandwiching a p-type body region (2), as well as a gate electrode (5a) which is opposed to p-type body region (2) sandwiching a gate insulating film (4a), and also has a stabilizing plate (5b). This stabilizing plate (5b) is made of a conductor or a semiconductor, is opposed to n⁻ silicon substrate (1) sandwiching an insulating film (4, 4b) for a plate, and forms together with n⁻ silicon substrate (1), a capacitor. This stabilizing plate capacitor formed between stabilizing plate (5b) and n⁻ silicon substrate (1) has a capacitance greater than that of the gate-drain capacitor formed between gate electrode (5a) and n⁻ silicon substrate (1).

Claims

1. A semiconductor device comprising:

an insulating gate type field effect transistor portion having a source region and a drain region separated from each other by a channel formation region, a gate electrode separated from said channel formation region by a gate insulating film; and

a stabilizing plate, made of a conductor or of a semiconductor, which is separated from said drain region by an insulating film, said stabilizing plate, drain region and insulating film therebetween forming a stabilizing plate capacitor;

wherein

said stabilizing plate capacitor has a capacitance greater than capacitance formed between said gate electrode and said drain region.

2. The semiconductor device according to claim 1, characterized in that said stabilizing plate is electrically connected to said source region.

3. The semiconductor device according to claim 1, characterized in that said stabilizing plate forms, together with the source potential, a capacitor.

4. The semiconductor device according to claim 1, characterized in that the film thickness of said insulating film for a plate in a portion where said stabilizing plate is opposed to said drain region is thinner than the film thickness of said gate insulating film in a portion where said gate electrode is opposed to said drain region.

5. The semiconductor device according to claim 1, characterized in that the dielectric constant of said insulating film for a plate in a portion where said stabilizing plate is opposed to said drain region is greater than the dielectric constant of said gate insulating film in a portion where said gate electrode is opposed to said drain region.

6. The semiconductor device according to claim 1, characterized in that

a plurality of transistors of the same type as said insulating gate type field effect transistor is arranged side by side, and

two or more plates of the same type as said stabilizing plate are arranged in a region sandwiched by two of said insulating gate type field effect transistors.

7. The semiconductor device according to claim 6, characterized in that the impurity concentration of a region in said drain region sandwiched by said two or more stabilizing plates is higher than the impurity concentration of the other regions in said drain region.

8. The semiconductor device according to claim 1, characterized by further comprising a semiconductor substrate having a first main surface and a second main surface that are opposed to each other and having a trench for a gate formed on said first main surface, wherein said gate electrode fills in said trench for a gate.

9. The semiconductor device according to claim 8, characterized in that said gate electrode has two sides opposed to each other and is opposed to said channel formation region in each of said two sides.

10. The semiconductor device according to claim 8, characterized in that said trench for a gate reaches to said drain region.

11. The semiconductor device according to claim 1, characterized in that an electrode on the source side is formed in the first main surface of said semiconductor substrate and an electrode on the drain side is formed in the second main surface of said semiconductor substrate.

12. The semiconductor device according to claim 1, characterized in that said channel formation region and said stabilizing plate exist within a region sandwiched between two adjacent gate electrodes.

13. A semiconductor device comprising:

an insulating gate type field effect transistor portion having a source region and a drain region separated from each other by a channel formation region, a gate electrode separated from said channel formation region by a gate insulating film;

a stabilizing plate, which is separated from said drain region by an insulating film, said stabilizing plate, drain region and insulating film therebetween forming a stabilizing plate capacitor; and

an impurity diffusion region surrounding a cell formation region having arranged therein a plurality of cells including said transistor portion, said impurity diffusion region being deeper than said channel formation region and opposite in conductivity to said source region and said drain region;

wherein said stabilizing plate is provided in said impurity diffusion region.

14. The semiconductor device according to claim 13, characterized in that a plurality of plates of the same type as said stabilizing plate is arranged adjacent to said arranged plurality of cells.