Low dielectric constant STI with SOI devices

• US 6,953,983 B2
• Filed: 12/08/2003
• Issued: 10/11/2005
• Est. Priority Date: 02/14/2000
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Farrar, Paul A.
• Primary Examiner(s): Jackson, Jerome
• Assistant Examiner(s): Fenty, Jesse A.
• Application Number:
  US10/730,641
• Publication Number:
  US 20040152278A1
• Time in Patent Office: 673 Days
• Field of Search: 257/522, 257/E21.564, 257/E21.573, 257/503, 257/506, 257347-354
• US Class Current: 257/522
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264

Abstract

Techniques of shallow trench isolation and devices produced therefrom are shown. The techniques of shallow trench isolation utilize foamed polymers, cured aerogels or air gaps as the insulation medium. Such techniques facilitate lower dielectric constants than the standard silicon dioxide due to the cells of gaseous components inherent in foamed polymers, cured aerogels or air gaps. Lower dielectric constants reduce capacitive coupling concerns and thus permit higher device density in an integrated circuit device. The shallow trench isolation structures are used on a variety of substrates including silicon-on-insulator (SOI) substrates and silicon-on-nothing (SON) substrates.

Claims

1. An integrated circuit device formed, comprising:

a substrate, including;

a dielectric layer including an air gap for location at least partially beneath an active region;

a semiconductor layer formed over the dielectric layer;

a first active region formed in the semiconductor layer;

a second active region formed in the semiconductor layer;

a trench formed in the substrate and interposed between the first active region and the second active region; and

wherein the trench contains cells of gaseous components and extends at least partially into a level of the dielectric layer of the substrate.

2. The integrated circuit device of claim 1, wherein the trench contains a fill material selected from the group consisting of a foamed polymeric material, a cured aerogel and an air gap.

3. The integrated circuit device of claim 2, wherein the foamed polymeric material comprises a polymeric material selected from the group consisting of methylsilsesquioxane, polyimides and polynorbornenes.

4. The integrated circuit device of claim 2, wherein the foamed polymeric material comprises a polymeric material selected from the group consisting of Type I and Type III polyimides.

5. The integrated circuit device of claim 1, wherein the semiconductor layer includes a silicon layer.

6. The integrated circuit device of claim 1, wherein the dielectric layer includes silicon dioxide (SiO₂).

7. An integrated circuit device, comprising:

a substrate, including;

a dielectric layer including an air gap for location at least partially beneath an active region;

a semiconductor layer formed over the dielectric layer;

a first active region formed in the semiconductor layer;

a second active region formed in the semiconductor layer;

a trench formed in the substrate and interposed between the first active region and the second active region; and

wherein the trench is filled with a foamed polymeric material and extends at least partially into a level of the dielectric layer of the substrate.

8. The integrated circuit device of claim 7, wherein the foamed polymeric material comprises a polymeric material selected from the group consisting of methylsilsesquioxane, polyimides and polynorbornenes.

9. The integrated circuit device of claim 7, wherein the foamed polymeric material comprises a polymeric material selected from the group consisting of Type I and Type III polyimides.

10. The integrated circuit device of claim 7, wherein the semiconductor layer includes a silicon layer.

11. The integrated circuit device of claim 7, wherein the dielectric layer includes silicon dioxide (SiO₂).

12. An integrated circuit device, comprising:

a substrate, including;

a dielectric layer including an air gap for location at least partially beneath an active region;

a semiconductor layer formed over the dielectric layer;

a first active region formed in the semiconductor layer;

a second active region formed in the semiconductor layer;

a trench formed in the substrate and interposed between the first active region and the second active region; and

wherein the trench is filled with a cured aerogel and extends at least partially into a level of the dielectric layer of the substrate.

13. The integrated circuit device of claim 12, wherein the semiconductor layer includes a silicon layer.

14. The integrated circuit device of claim 12, wherein the dielectric layer includes silicon dioxide (SiO₂).

15. An integrated circuit device, comprising:

a substrate, including;

a dielectric layer including an air gap for location at least partially beneath an active region;

a semiconductor layer formed over the dielectric layer;

a first active region formed in the semiconductor layer;

a second active region formed in the semiconductor layer;

a trench formed in the substrate and interposed between the first active region and the second active region; and

wherein the trench is filled with an air gap and extends at least partially into a level of the dielectric layer of the substrate.

16. The integrated circuit device of claim 15, wherein the semiconductor layer includes a silicon layer.

17. The integrated circuit device of claim 15, wherein the dielectric layer includes silicon dioxide (SiO₂).

18. An integrated circuit device, comprising:

a substrate, including;

a dielectric layer formed within a portion of a semiconductor layer, the dielectric layer including an air gap for location at least partially beneath an active region;

a first transistor formed in the semiconductor layer;

a second transistor formed in the semiconductor layer; and

a trench formed in the substrate and interposed between the first transistor and the second transistor, wherein the trench contains cells of gaseous components.

19. The integrated circuit device of claim 18, wherein the trench contains a fill material selected from the group consisting of a foamed polymeric material, a cured aerogel and an air gap.

20. The integrated circuit device of claim 19, wherein the foamed polymeric material comprises a polymeric material selected from the group consisting of methylsilsesquioxane, polyimides and polynorbornenes.

21. The integrated circuit device of claim 18, wherein the dielectric layer includes silicon dioxide (SiO₂).

22. A memory system, comprising:

a substrate, including;

a dielectric layer including an air gap for location at least partially beneath an active region;

a semiconductor layer formed over the dielectric layer;

a first number of transistors formed in the semiconductor layer;

a second number of transistors formed in the semiconductor layer;

a trench formed in the substrate and interposed between the first number of transistors and the second number of transistors; and

wherein the trench contains cells of gaseous components and extends at least partially into a level of the dielectric layer of the substrate.

23. The memory system of claim 22, wherein the trench contains a fill material selected from the group consisting of a foamed polymeric material, a cured aerogel and an air gap.

24. The memory system of claim 22, wherein trench contains a foamed polymeric material selected from the group consisting of methylsilsesquioxane, polyimides and polynorbornenes.

25. The memory system of claim 22, wherein the dielectric layer includes silicon dioxide (SiO₂).

26. A computer system, comprising:

a memory system, including;

a substrate, including;

a dielectric layer including an air gap for location at least partially beneath an active region;

a semiconductor layer formed over the dielectric layer;

a first active region formed in the semiconductor layer;

a second active region formed in the semiconductor layer;

a trench formed in the substrate and interposed between the first active region and the second active region, wherein the trench contains cells of gaseous components and extends at least partially into a level of the dielectric layer of the substrate; and

a processor coupled to the first and second electronic devices.

27. The computer system of claim 26, wherein the trench contains a fill material selected from the group consisting of a foamed polymeric material, a cured aerogel and an air gap.

28. The computer system of claim 27, wherein the foamed polymeric material comprises a polymeric material selected from the group consisting of methylsilsesquioxane, polyimides and polynorbornenes.

29. The computer system of claim 26, wherein the dielectric layer includes silicon dioxide (SiO₂).