Wafer level MEMS packaging

• US 6,953,985 B2
• Filed: 06/12/2002
• Issued: 10/11/2005
• Est. Priority Date: 06/12/2002
• Status: Expired due to Fees

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: De Silva, Ananda P., Lin, Jong-Kai, Lytle, William H., Fay, Owen, Markgraf, Steven, Hughes, Henry G., Amrine, Craig
• Primary Examiner(s): Zarneke, David A.
• Application Number:
  US10/170,184
• Publication Number:
  US 20030230798A1
• Time in Patent Office: 1,217 Days
• Field of Search: 257/659, 257/660, 257/704, 257/708, 257/710, 438/106, 438/121, 438/125
• US Class Current: 257/659
• CPC Class Codes: B81B 7/0064 for protecting against electromagnetic or electrostatic interferences
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/11901 with repetition of the same manufacturing step
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01022 Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01024 Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0104 : Zirconium [Zr]
• CPC Class Codes: H01L 2924/01041 : Niobium [Nb]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1423 : Monolithic Microwave Integrated Circuit [MMIC]
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

An exemplary method and apparatus for MEMS device wafer level and/or array packaging comprises inter alia an EM shielding array of dielectric lid elements (340) sealed to a MEMS device die array (300) to produce a sealed MEMS device package array (330). Disclosed features and specifications may be variously controlled, adapted or otherwise optionally modified to improve hermetic sealing and/or EM shielding for any MEMS device. An exemplary embodiment of the present invention representatively provides for wafer level packaging of RF MEMS switches prior to device singulation.

Claims

1. A device packaging element comprising:

a dielectric lid;

said dielectric lid comprising at least one of;

an insulating layer and a conductive layer;

said dielectric lid suitably adapted for effectively enclosing a MEMS device on a device substrate, wherein engagement or said dielectric lid with said device substrate defines a MEMS device enclosure; and

said dielectric lid suitably adapted to effectively shield said MEMS device from at least one of electromagnetic (EM) energy incident to said device enclosure and leakage of EM energy from said device enclosure.

2. The device packaging element of claim 1, wherein:

said insulating layer comprises at least one of GaAs, silicon, quartz, glass, sapphire and ceramic; and

said conductive layer comprises at least one of Ag, Al, Au, Cr, Cu, Hf, Mo, Nb, Ni, Pb, Pd, Sn, Ta, Ti, V, W, Zr, a metal and a metal alloy.

3. The device packaging element of claim 1, wherein;

said EM energy comprises radio frequency (RF) energy; and

said dielectric lid further comprises a seal suitably adapted for effectively sealing said dielectric lid to said device substrate.

4. The device packaging element of claim 3, wherein:

said seal comprises a conductive seal; and

at least one of said conductive seal and said conductive layer are connected to ground.

5. The device packaging element of claim 4, wherein:

said connection to ground comprises a device common ground connection through an interconnect of said device substrate; and

wherein said MEMS device comprises an RF MEMS switch.

6. An EM shielded MEMS device package, comprising:

a device die comprising a MEMS device;

a dielectric lid, wherein said dielectric lid comprises a metal layer;

said dielectric lid suitably adapted for effectively enclosing said MEMS device on said device die; and

said dielectric lid suitably adapted to effectively shield said MEMS device from at least one of EM energy incident to said device package and leakage of EM energy from said device package.

7. The device package of claim 6, further comprising:

a seal comprising at least one of a hermetic seal and a conductive seal; and

said seal disposed substantially between said dielectric lid and said device die.

8. The device package of claim 7, wherein:

said EM energy comprises RF energy; and

said seal comprises solder.

9. The device package of claim 8, wherein:

said metal layer comprises TiW; and

at least one of said solder seal and said TiW layer are connected to ground.

10. The device package of claim 9, wherein:

said connection to ground comprises a device common ground connection through an interconnect of said device substrate; and

said MEMS device comprises an RF MEMS switch.

11. A MEMS device array package, comprising:

an array of device dies, each die comprising a MEMS device;

an array of dielectrics lids;

said lid array suitably adapted for effectively enclosing said MEMS devices; and

wherein said dielectric lids include conductive layers;

an array of seals;

said seals disposed substantially between said dielectric lids and said device dies to form an array of discretely sealed MEMS device elements in a package array; and

said dielectric lids suitably adapted to effectively shield said MEMS devices from at least one of EM energy incident to said sealed MEMS devices and leakage of EM energy from said sealed MEMS devices.

12. The array package of claim 11, wherein:

said EM energy comprises RF energy;

said dielectric lid comprises an array of RF shielding regions;

said RF shielding regions comprising a conductive layer wherein the surface areas of the RF shielding regions effectively correspond to the surface areas of the MEMS device dies; and

said RF shielding regions are substantially aligned with said device dies.

13. The array package of claim 12, wherein at least one of said seals and said RF shielding regions are connected to ground.

14. The array package of claim 13, wherein:

said connections to ground comprise device common ground connections through an interconnect of said device dies; and

said MEMS devices comprise RF MEMS switches.

15. A method for MEMS device packaging, comprising the steps of:

providing a device die comprising a MEMS device;

providing a dielectric lid;

said dielectric lid comprising at least one of;

an insulating layer and a conductive layer;

said dielectric lid suitably adapted to effectively shield said MEMS device from at least one of EM energy incident to said device package and leakage of EM energy from said device package; and

hermetically sealing said dielectric lid to said device die so as to form a substantially enclosed MEMS device package.

16. The method for MEMS device packaging of claim 15, wherein:

said insulating layer comprises at least one of GaAs, silicon, quartz, glass, sapphire and ceramic;

said conductive layer comprises at least one of Ag, Al, Au, Cr, Cu, Hf, Mo, Nb, Ni, Pb, Pd, Sn, Ta, Ti, V, W, Zr, a metal and a metal alloy;

said hermetic seal further comprises a conductive seal;

at least one of said conductive seal and said conductive layer are connected to a device common ground;

said EM energy comprises RF energy; and

said MEMS device comprises an RF MEMS switch.

17. A method for MEMS device wafer level packaging, comprising the steps of:

providing at least an array of device dies, each die comprising at least one MEMS device;

providing an array of dielectric lids wherein said dielectric lid array elements comprise at least one of;

an insulating layer and a conductive layer;

providing at least an array of seals, each of said seals disposed substantially annularly around each of said MEMS devices in said die array such that each of said device die elements is substantially peripherally bounded by at least one of said seals;

hermetically sealing said dielectric lid to said device die array elements so as to form discretely sealed MEMS device elements in a wafer package array; and

said dielectric lid suitably adapted to substantially shield said MEMS devices from at least one of EM energy incident to said sealed MEMS device elements and leakage of EM energy from said sealed MEMS device elements.

18. The method for MEMS device wafer level packaging of claim 17, wherein:

said insulating layer comprises at least one of GaAs, silicon, quartz, glass, sapphire and ceramic;

said conductive layer comprises at least one of Ag, Al, Au, Cr, Cu, Hf, Mo, Nb, Ni, Pb, Pd, Sn, Ta, Ti, V, W, Zr, a metal and a metal alloy;

said hermetic seal further comprises a conductive seal;

at least one of said conductive seal and said conductive layer are connected to a device common ground;

said EM energy comprises RF energy; and

said MEMS device comprises an RF MEMS switch.

19. The method for MEMS device wafer level packaging of claim 17, wherein:

said dielectric lid further comprises an array of EM shielding regions;

the surface area of said EM shielding region array elements effectively corresponding to the surface area of said device die array elements; and

said method for wafer level packaging further comprising the step of substantially aligning said EM shielding array elements with said device die array elements substantially prior to sealing said dielectric lid to said device die array.

20. A method for making an EM shielding package lid suitable for wafer level MEMS device packaging, comprising the steps of:

providing a dielectric lid substrate;

depositing a shielding metal layer over said substrate;

wherein said shielding metal layer substantially shields EM energy;

depositing at least one layer of photoresist over said metal layer;

patterning said photoresist to at least partially expose a window to one of said metal layers;

electroplating at least a solder wettable material into said exposed window;

at least one of;

electroplating solder over said solder wettable metal and stripping said photoresist to substantially expose at least a portion of a metal layer;

at least one of;

stripping said photoresist to substantially expose at least a portion of a metal layer and etching an exposed metal layer; and

at least one of;

optionally etching an exposed metal layer and depositing solder over said solder wettable metal.

21. The method for making an EM shielding package lid of claim 20, wherein said insulating substrate is at least one of GaAs, silicon, quartz, glass, sapphire and ceramic.

22. The method for making an EM shielding package lid of claim 20, wherein said metal layer comprises at least one of Al, Au, Cr, Cu, Pb, Sn, Ti, W, a metal and a metal alloy.

23. The method for making an EM shielding package lid of claim 20, wherein said patterning of said photoresist is accomplished photolithographically.

24. The method for making an EM shielding package lid of claim 20, wherein said solder wettable material comprises at least one of Cu and Au.

25. The method for making an EM shielding package lid of claim 20, wherein said solder comprises at least one of Cu, Pb and Sn.

26. A method for MEMS device packaging, comprising the steps of:

providing a plurality of MEMS devices;

providing a substrate with an array of device die recesses;

said device recesses annularly defined by peripheral frames, said device recesses suitably adapted for disposing said MEMS devices therein;

providing an array of dielectric lids comprising an insulating substrate with at least an array or cells;

said insulating substrate cell array defining a plurality of EM shielding lid regions, said substrate cell array lid regions further comprising an array of peripheral frames;

depositing at least one metal film layer over said insulating substrate;

lithographically processing said insulating substrate to expose said lid region peripheral frames;

depositing a solder-wettable material to a desired thickness over at least one of said device cell peripheral frames and lid region peripheral frames;

depositing solder to a desired thickness over said solder-wettable material;

aligning at least one of said wafer cell array and said insulating substrate array; and

reflowing said solder to seal said device die cells to said lid cells.

27. The method for MEMS device packaging of claim 26, further comprising the step of dicing sealed device elements.

28. The method for MEMS device packaging of claim 26, further comprising the step of grounding at least one of said solder seal and said metal film.

29. The method for MEMS device packaging of claim 28, wherein:

said insulating layer comprises at least one of GaAs, silicon, quartz, glass, sapphire and ceramic;

said metal film comprises at least one of Al, Au, Cr, Cu, Pb, Sn, Ti, W, a metal and a metal alloy;

said EM shielding comprises RF shielding;

said MEMS device comprises an RF MEMS switch; and

said grounding comprises conductive connection to a ground plane in at least one of a redistribution layer and a ground region in a multilayer ceramic structure.