Semiconductor package

• US 6,953,988 B2
• Filed: 09/17/2004
• Issued: 10/11/2005
• Est. Priority Date: 03/25/2000
• Status: Expired due to Term

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Yee, Jae Hak, Chung, Young Suk, Ku, Jae Hun, Paek, Jong Sik, Seo, Seong Min
• Primary Examiner(s): CLARK, JASMINE JHIHAN B
• Application Number:
  US10/944,241
• Publication Number:
  US 20050062148A1
• Time in Patent Office: 389 Days
• Field of Search: 257/666, 257/670, 257/671, 257/788, 257/796, 257/783
• US Class Current: 257/666
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16245 the item being metallic
• CPC Class Codes: H01L 2224/29101 the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/8319 Arrangement of the layer connectors prior to mounting
• CPC Class Codes: H01L 2224/838 Bonding techniques
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/4951 Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
• CPC Class Codes: H01L 23/49548 Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0781 : being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A semiconductor package is disclosed that bonds a semiconductor chip to a leadframe using a flip chip technology. An exemplary semiconductor package includes a semiconductor chip having a plurality of input-output pads at an active surface thereof. A plurality of leads are superimposed by the bond pads and active surface of the semiconductor chip. The leads have at least one exposed surface at a bottom surface of the package body. A plurality of conductive connecting means electrically connect the input-output pads of the chip to the leads. A package body is formed over the semiconductor chip and the conductive connecting means. The bottom surface portions of the leads are exposed to the outside.

Claims

1. A semiconductor package comprising:

a plurality of leads, each lead having a first side, and an opposite second side having at least one first surface and at least one second surface recessed from the first surface;

a chip mounting substrate having a first side and an opposite second side, the second side having a central surface and a peripheral surface recessed from the central surface;

a semiconductor chip having an active surface facing the first side of the leads and the first side of the chip mounting substrate, and peripheral input-output pads at a peripheral portion of the active surface, wherein each of the peripheral input-output pads faces and is electrically connected to the first side of a respective one of the leads; and

a package body formed of a hardened encapsulating material, wherein the encapsulating material covers the semiconductor chip, the recessed peripheral surface of the second side of the chip mounting substrate, and the at least one recessed second surface of the second side of each of the leads, while the central surface of the second side of the chip mounting substrate and the at least one first surface of the second side of each of the leads are exposed at a first exterior surface of the package body.

2. The semiconductor package of claim 1, wherein the second side of each of the leads includes a plurality of the first surfaces and second surfaces, and the first surfaces of the leads collectively form rows and columns at the first exterior surface of the package body.

3. The semiconductor package of claim 1, wherein a surface of the semiconductor chip is exposed at an exterior surface of the package body.

4. The semiconductor package of claim 1, wherein the active surface of the semiconductor chip includes at least one central input-output pad inward of the peripheral input-output pads, and the at least one central input-output pad faces and is electrically connected to the first side of the chip mounting substrate.

5. The semiconductor package of claim 4, wherein each of the peripheral input-output pads is electrically connected to the first side of a respective one of the leads by at least one of a plurality of reflowed metal balls, and the at least one central input-output pad is electrically connected to the first side of the chip mounting substrate by at least one of the plurality of reflowed metal balls.

6. The semiconductor package of claim 5, further comprising a discrete insulative layer on the first side of each of the leads and the first side of the chip mounting substrate, wherein each of the insulative layers is covered by the encapsulating material and each of the reflowed metal balls extends through an opening in a respective one of the insulative layers.

7. The semiconductor package of claim 4, wherein each of the peripheral input-output pads is electrically connected to the first side of a respective one of the leads by at least one of a plurality of anisotropic conductive films, and the at least one central input-output pad is electrically connected to the first side of the chip mounting substrate by at least one of a plurality of anisotropic conductive films.

8. The semiconductor package of claim 1, wherein each of the peripheral input-output pads is electrically connected to the first side of a respective one of the leads by a reflowed metal ball.

9. The semiconductor package of claim 8, further comprising a discrete insulative layer on the first side of each of the leads, wherein each of the insulative layers is covered by the encapsulating material and each of the reflowed metal balls extends through an opening in a respective one of the insulative layers.

10. The semiconductor package of claim 1, wherein each of the peripheral input-output pads is electrically connected to the first side of a respective one of the leads by an anisotropic conductive film.

11. The semiconductor package of claim 1, further comprising a conductive ball fused to each exposed first surface of the second side of each of the leads.

12. The semiconductor package of claim 2, comprising a conductive ball fused to each exposed first surface of the second side of each of the leads.

13. The semiconductor package of claim 11, wherein one of a conductive paste and a plurality of conductive balls are on the central surface of the second side of the chip mounting substrate.

14. A semiconductor package comprising:

a plurality of leads, each lead having a first side, and an opposite second side having at least one first surface and at least one second surface recessed from the first surface;

a chip mounting substrate having a first side and an opposite second side, the second side having a central surface and a peripheral surface recessed from the central surface;

a semiconductor chip in a flip chip electrical connection with the first side of at least some of the leads and the first side of the chip mounting substrate; and

a package body formed a hardened encapsulating material, wherein the encapsulating material covers the semiconductor chip, the recessed peripheral surface of the second side of the chip mounting substrate, and the recessed second surface of the second side of each of the leads, while the central surface of the second side of the chip mounting substrate and the at least one first surface of the second side of each of the leads are exposed at a first exterior surface of the package body.

15. The semiconductor package of claim 14, further comprising a discrete insulative layer on the first side of each of the leads and the first side of the chip mounting substrate, wherein each of the insulative layers is covered by the encapsulating material, and the semiconductor chip is electrically connected to the first side of each of the leads and the first side of the chip mounting substrate through openings in respective ones of the insulating layers.

16. A semiconductor package comprising:

a plurality of leads, each lead having a first side, and an opposite second side having at least one first surface and at least one second surface recessed from the first surface;

a chip mounting substrate having a first side and an opposite second side, the second side having a central surface and a peripheral surface recessed from the central surface;

a plurality of insulative layers on respective ones of the first sides of the leads and the first side of the chip mounting substrate;

a semiconductor chip in a flip chip electrical connection with the first side of at least some of the leads and the first side of the chip mounting substrate through respective ones of the insulative layers; and

a package body formed of a hardened encapsulating material, wherein the encapsulating material covers the semiconductor chip and the insulative layers, the recessed peripheral surface of the second side of the chip mounting substrate, and the recessed second surface of the second side of each of the leads, while the central surface of the second side of the chip mounting substrate and the at least one first surface of the second side of the leads are exposed at a first exterior surface of the package body.