Process for automatically generating several electrical pulses using numeric default values, in particular for simulating an incremental encoder
First Claim
1. A digital electronic data processing apparatus for automatically generating several electrical pulses (8a, 8b, 8c) or pulse flanks using numeric default values (L(Ta)), in particular for simulating an incremental encoder for a sequential, digital counting of linear or angular displacement values using said pulses or pulse flanks, comprising one or more data registers (10, 11) working time-discretely, which can be loaded and read repeatedly at equidistant transmission times with said generated default values (L(Ta)) and other parameters (k), further comprising a calculation and control system which is designed for access to the one or more data registers (10, 11) and to process content of the one or more data registers including said default values (L(Ta)) and parameters (k), and further comprising a pulse generation logic (17, 19, 21) which can be triggered by said calculation and control system and is designed to output pulse-like binary switching states (8a, 8b, 8c), characterized in that said calculation and control system is designed in programming or circuitry to be a sampling system based on repeated first sampling cycle times (Ta) comprising the following functions:
- (a) periodical time-discrete access to the one or more data registers (10, 11) within time periods between said transmission times of said default values out of the one or more data registers (10, 11), said time periods corresponding to said first cycle times (Ta), (b) determining a difference value (Δ
L) from one of the current default values (L(Ta)) and an incremental value (L(Tk)), said incremental value (L(Tk)) having been tracked in said calculation and control system from previous ones of said default values (L(Ta)), (c) breaking down said difference value (Δ
L) into individual sum part values such that their number corresponds to the ratio (k) of said first sampling cycle time to a repeated second cycle time (Tk), said incremental value (L(Tk)) being counted upwards or downwards using one of said sum part values within one of said second cycle times (Tk) each, and (d) triggering a pulse generation logic (17, 19, 21) within each of said second cycle times (Tk) dependent on any increase or decrease of said incremental value (L(Tk)) in the course of its above-mentioned tracking to output corresponding pulse-like binary switching states.
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Abstract
The invention relates to a method for automatically generating several electrical pulses using numeric default values, in particular for simulating an incremental encoder for a sequential, digital counting of linear or angular displacement values using said pulses. The method incorporates a value generator that outputs the default values repeatedly within each first cycle time, calculation and control means that detect the default values in a cyclic manner and a pulse switching interface that has one or more outputs for the pulses. The program and/or circuitry of the calculation and control means are designed:—for detecting the respective current default value and for determining a differential value from the current and preceding default value or incremental value for each first cycle time, said value having been previously counted in ascending or descending order, according to preceding default values,—for converting the differential value into control signals for the pulse switching interface within several second cycle times, whose total duration does not exceed the first cycle time of the value generator,—and for measuring the number or frequency of the pulses or pulse edges, according to the respective differential value.
5 Citations
7 Claims
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1. A digital electronic data processing apparatus for automatically generating several electrical pulses (8a, 8b, 8c) or pulse flanks using numeric default values (L(Ta)), in particular for simulating an incremental encoder for a sequential, digital counting of linear or angular displacement values using said pulses or pulse flanks, comprising one or more data registers (10, 11) working time-discretely, which can be loaded and read repeatedly at equidistant transmission times with said generated default values (L(Ta)) and other parameters (k), further comprising a calculation and control system which is designed for access to the one or more data registers (10, 11) and to process content of the one or more data registers including said default values (L(Ta)) and parameters (k), and further comprising a pulse generation logic (17, 19, 21) which can be triggered by said calculation and control system and is designed to output pulse-like binary switching states (8a, 8b, 8c), characterized in that said calculation and control system is designed in programming or circuitry to be a sampling system based on repeated first sampling cycle times (Ta) comprising the following functions:
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(a) periodical time-discrete access to the one or more data registers (10, 11) within time periods between said transmission times of said default values out of the one or more data registers (10, 11), said time periods corresponding to said first cycle times (Ta), (b) determining a difference value (Δ
L) from one of the current default values (L(Ta)) and an incremental value (L(Tk)), said incremental value (L(Tk)) having been tracked in said calculation and control system from previous ones of said default values (L(Ta)),(c) breaking down said difference value (Δ
L) into individual sum part values such that their number corresponds to the ratio (k) of said first sampling cycle time to a repeated second cycle time (Tk), said incremental value (L(Tk)) being counted upwards or downwards using one of said sum part values within one of said second cycle times (Tk) each, and(d) triggering a pulse generation logic (17, 19, 21) within each of said second cycle times (Tk) dependent on any increase or decrease of said incremental value (L(Tk)) in the course of its above-mentioned tracking to output corresponding pulse-like binary switching states. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Specification