Semiconductor integrated circuit device

• US 6,954,371 B2
• Filed: 06/04/2004
• Issued: 10/11/2005
• Est. Priority Date: 07/29/2003
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Hasegawa, Masatoshi, Tanaka, Yousuke, Hokari, Tomofumi
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US10/860,770
• Publication Number:
  US 20050024949A1
• Time in Patent Office: 494 Days
• Field of Search: 365/149, 365/203, 365/210
• US Class Current: 365/149
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 11/4099 Dummy cell treatment; Reference voltage generators
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

The present invention provides a dynamic RAM which can be operated at a low voltage and realizes the enhancement of a read margin and an area-saving layout. In a memory array including a plurality of memory cells having capacitors which are formed corresponding to a plurality of word lines and a plurality of bit lines, stored information of the memory cell which is read to one bit line out of the pair of bit lines is sensed by a sense amplifier in response to a reference voltage which is formed by a dummy cell connected to another bit line, a precharge voltage of high level or low level corresponding to an operational voltage by a precharge circuit is supplied to the bit lines, and the dummy cells having the same structure as the memory cells are formed at crossing points of word lines for dummy cells and bit lines arranged outside the memory array, MOSFETs which precharge an intermediate voltage between the high level voltage and the low level voltage to the capacitors are provided, and gates of the MOSFETs are connected with charge word lines for dummy cells which are extended in parallel with the word lines for dummy cells.

Claims

1. A semiconductor integrated circuit device having a memory circuit comprising:

a memory array including a plurality of memory cells having stack-type capacitors which are formed corresponding to a plurality of word lines and a plurality of bit lines;

a sense amplifier which is provided corresponding to a pair of bit lines and senses and amplifies stored information of a memory cell of the plurality of memory cells which is read to one bit line in response to a reference voltage formed in a dummy cell, of a plurality of dummy cells, which is connected to another bit line; and

a precharge circuit which supplies a precharge voltage of high level or low level corresponding to an operational voltage of the sense amplifier to the bit lines, wherein

the plurality of dummy cells have the same structure as the plurality of memory cells and are formed at crossing points of dummy cell word lines and the bit lines, the plurality of dummy cells being provided at the outside of the memory array, and

MOSFETs which precharge an intermediate voltage between the high level voltage and the low level voltage are provided to storage nodes of the stack-type capacitors of the dummy cells, and gates of the MOSFETs are connected with charge word lines for dummy cells which are extended in parallel with the word lines for dummy cells.

2. A semiconductor integrated circuit device according to claim 1, wherein the dummy cell word lines and the dummy cell charge word lines are connected with word lines in the memory array and are repeatedly formed at the same line pitch.

3. A semiconductor integrated circuit device according to claim 2, wherein diffusion layers to which the intermediate voltage is applied are provided outside the dummy cell word lines and the dummy cell charge word lines, and sources and drains of the MOSFETs at one side are formed such that the sources and drains extend to the diffusion layers.

4. A semiconductor integrated circuit device according to claim 3, wherein the diffusion layers are used also as guard rings of the memory array.

5. A semiconductor integrated circuit device according to claim 4, wherein the dummy cell word lines and the dummy cell charge word lines are driven by a selective circuit which has the circuit constitution equal to the circuit constitution of a word driver which selects the word lines of the memory array.

6. A semiconductor integrated circuit device according to claim 5, wherein the dummy cell charge word lines are set to a selective level and make the MOSFETs assume an ON state only during a specific dummy cell charging period within a precharge period of a precharge circuit provided to the bit lines and are set to a non-selective state in other period.

7. A semiconductor integrated circuit device according to claim 6, wherein the MOSFETs of the selective circuits which drive the dummy cell charge word lines are formed to have a channel length larger than a channel length of MOSFETs which constitute the word driver.

8. A semiconductor integrated circuit device according to claim 4, wherein the guard ring portions of the memory array which are used also for charging the dummy cells have only read portions extended from the diffusion layers formed into silicide.

9. A semiconductor integrated circuit device according to claim 3, wherein the memory array adopts a two crossing-point method in which the pair of bit lines are extended in parallel,

the dummy cells, the dummy cell word lines and the dummy cell charge word lines which correspond to one bit line are arranged at one end side of the memory array in the bit line direction,

the dummy cells, the dummy cell word lines and the dummy cell charge word lines which correspond to another pair of bit lines are arranged at another end side of the memory array in the bit line direction, and

the diffusion layers each of which is arranged between the diffusion layers which are formed by extending one of the source and the drain of the MOSFET are not provided, plugs are provided, and contact portions are not provided.

10. A semiconductor integrated circuit device according to claim 3, wherein the memory array adopts a one crossing-point method in which the pair of bit lines are extended at both sides of the sense amplifier, and the dummy cells, the dummy cell word lines and the dummy cell charge word lines are arranged close to the sense amplifier.