Methods and systems for sending side-channel data during data inactive period
First Claim
1. A high speed digital transmitter capable of sending side channel data, the transmitting comprising:
- a channel zero encoder having first and second inputs and an output, the first input receiving channel zero primary data, the second input receiving a channel zero DEout signal, and the output producing channel zero encoded data, the channel zero encoder operative to produce channel zero encoded data based at least in part on the channel zero primary data and the channel zero DEout signal;
a channel one multiplexer having at least first and second data inputs, at least one control input, and at least one output, the channel one multiplexer operative to multiplex channel one primary data and channel one side channel data, the first data input receiving channel one primary data, the control input receiving a DEI signal, and the output providing a multiplexed signal including channel one side channel data and channel one primary data;
a channel one DEout control logic having a first input and an output, the channel one DEout control logic operative to produce a channel one DEout signal for facilitating transfer of channel one side channel data, the first input receiving a DEI signal, and the output producing a channel one DEout signal; and
a channel one encoder having first and second inputs and an output, the first input receiving the output of the channel one multiplexer, the second input receiving the output of the channel one DEout control logic, the output producing channel one encoded data, the channel one encoder operative to produce channel one encoded data based at least in part on the first and second inputs.
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Abstract
The present invention relates to a serial interface transmission system with more than one data line, in which the transmitted data has in-band and out-of-band characters. More particularly, the present invention relates to methods and systems for sending side channel data over a high-speed digital communications link, e.g., a video link. One embodiment of the invention provides a high-speed digital transmitter capable of sending side channel data. The transmitter includes a channel zero encoder, a multiplexer, data enable out (DEout) control logic, and a channel one encoder. The channel one encoder receives input from the channel one multiplexer and the channel one DEout control logic. Another embodiment of the invention provides a high-speed digital receiver capable of receiving side channel data. The receiver includes a channel zero decoder, a channel one decoder, DEI signal and FIFO control signal recovery logic, and a channel one de-multiplexer. The DEI signal and FIFO control signal recovery logic receives input from the channel one decoder. Similarly, the channel one demultiplexer receives input from the channel one decoder.
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Citations
27 Claims
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1. A high speed digital transmitter capable of sending side channel data, the transmitting comprising:
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a channel zero encoder having first and second inputs and an output, the first input receiving channel zero primary data, the second input receiving a channel zero DEout signal, and the output producing channel zero encoded data, the channel zero encoder operative to produce channel zero encoded data based at least in part on the channel zero primary data and the channel zero DEout signal; a channel one multiplexer having at least first and second data inputs, at least one control input, and at least one output, the channel one multiplexer operative to multiplex channel one primary data and channel one side channel data, the first data input receiving channel one primary data, the control input receiving a DEI signal, and the output providing a multiplexed signal including channel one side channel data and channel one primary data; a channel one DEout control logic having a first input and an output, the channel one DEout control logic operative to produce a channel one DEout signal for facilitating transfer of channel one side channel data, the first input receiving a DEI signal, and the output producing a channel one DEout signal; and a channel one encoder having first and second inputs and an output, the first input receiving the output of the channel one multiplexer, the second input receiving the output of the channel one DEout control logic, the output producing channel one encoded data, the channel one encoder operative to produce channel one encoded data based at least in part on the first and second inputs. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A high-speed digital receiver capable of receiving side channel data, the receiver comprising:
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a channel zero decoder having a first input and second outputs, the first input receiving channel zero encoded data, the first output producing a channel zero decoded data signal, the second output producing a channel zero DEout signal, the channel zero decoder operative to produce channel zero decoded data and a channel zero DEout signal from the channel zero encoded data; a channel one decoder having at least an input and first and second outputs, the first input receiving channel one encoded data, the first output producing channel one decoded data, the second output producing a channel one DEout signal, the channel one decoder operative to produce channel one decoded data and a channel one DEout signal from the channel one encoded data; a DEI signal and a FIFO control signal recovery logic having first and second inputs and first and second outputs, the first input receiving the channel zero DEout signal, the second input receiving the channel one DEout signal, the DEI signal and FIFO control signal recovery logic operative to derive a DEI signal, the first output producing a DEI signal, the second output producing a first FIFO control signal; and a channel one de-multiplexer having a data input, a control input, and first and second outputs, the channel one de-multiplexer operative to separate channel one decoded data into channel one primary data and channel one side channel data, the data input receiving channel one decoded data from the channel one decoder, the control input receiving the DEI signal from the DEI signal and FIFO control signal recovery logic, the first output producing channel one side channel data, and the second output producing channel one primary data. - View Dependent Claims (12, 13, 14)
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15. A method for sending side channel data, the method comprising:
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encoding channel zero primary data for transmission using a channel zero encoder having first and second inputs and one output, the first input receiving channel zero primary data, the second input receiving a channel zero DEout signal, and the output producing channel zero encoded data, the channel zero encoder operative to produce channel zero encoded data based at least in part on the channel zero primary data and the channel zero DEout signal; multiplexing channel one primary data and channel one side channel data using a channel one multiplexer having first and second data inputs, a control input, and an output, the first data input receiving channel one primary data, the second data input receiving channel one side channel data, the control input receiving a DEI signal, and the output providing channel one side channel data or channel one primary data depending on the value of the DEI signal; producing a channel one DEout signal from facilitating transfer of channel one side channel data using channel one DEout control logic having an input and an output, the first input receiving a DEI signal, and the output producing a channel one DEout signal; and encoding channel one data for transmission using a channel one encoder having first and second inputs and an output, the first input receiving the output of the channel one multiplexer, the second input receiving the output of the channel one DEout control logic, the output producing channel one encoded data based at least in part on the two inputs.
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16. A method for receiving side channel data, the method comprising:
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receiving channel zero encoded data and channel one encoded data; decoding channel zero encoded data using a channel zero decoder having a first input and first and second outputs, the first input receiving channel zero encoded data, the first output producing a channel zero decoded data signal, the second output producing a channel zero DEout signal; decoding channel one encoded data using a channel one decoder having at least an input and first and second outputs, the first input receiving channel one encoded data, the first output producing channel one decoded data, the second output producing a channel one DEout signal; deriving a DEI signaling using a DEI signal and FIFO control signal recovery logic having first and second inputs and first and second outputs, the first input receiving the channel zero DEout signal, the second input receiving the channel one DEout signal, the first output producing a DEI signal, the second output producing a first FIFO control signal; and separating channel one decoded data from channel one side channel data using a channel one de-multiplexer having a data input, a control input, and first and second outputs, the data input receiving channel one decoded data from the channel one decoder, the control input receiving the DEI signal from the DEI signal and FIFO control signal recovery logic, the first output producing channel one side channel data, and the second output producing channel one primary data.
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17. A high speed digital transmission system capable of sending side channel, the system comprising:
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a transmitter having first and second outputs, a receiver having first and second inputs, a channel zero connecting the first output of the transmitter to the first input of the receiver, and a channel one connecting the second output of the transmitter to the second input of the receiver; wherein the transmitter comprises;
a channel zero encoder having first and second inputs an and output, the first input receiving channel zero primary data, the second input receiving a channel zero DEout signal, and the output producing channel zero encoded data, the channel zero encoder operative to produce channel zero encoded data based at least in part on the channel zero primary data and the channel zero DEout signal;a channel one multiplexer having first and second data inputs, a control input, and an output, the channel one multiplexer operative to multiplex channel one primary data and channel one side channel data, the first data input receiving channel one primary data, the second data input receiving channel one side channel data, the control input receiving a DEI signal, and the output providing channel one side channel data or channel one primary data depending on the value of the DEI signal; a channel one DEout control logic having an input and an output, the channel one DEout control logic operative to produce a channel one DEout signal for facilitating transfer of channel one side channel data, the first input receiving a DEI signal, and the output producing a channel one DEout signal; and a channel one encoder having two inputs and one output, the first input receiving the output of the channel one multiplexer, the second input receiving the output of the channel one DEout control logic, the output producing channel one encoded data the channel one encoder operative to produce channel one encoded data based at least in part on the two inputs; and wherein the receiver comprises;
a channel zero decoder having an input and first and second outputs, the first input receiving channel zero encoded data, the first output producing a channel zero decoded data signal, the second output producing a channel zero DEout signal, the channel zero decoder operative to produce channel zero decoded data and a channel zero DEout signal from the channel zero encoded data;a channel one decoder having at least one input and at least first and second outputs, the first input receiving channel one encoded data, the first output producing channel one decoded data, the second output producing a channel one DEout signal, the channel one decoder operative to produce channel one decoded data and a channel one DEout signal from the channel one encoded data; a DEI signal and a FIFO control signal recovery logic having first and second inputs and first and second outputs, the first input receiving the channel zero DEout signal, the second input receiving the channel one DEout signal, the DEI signal and FIFO control signal recovery logic operative to derive a DEI signal, the first output producing a DEI signal, the second output producing a first FIFO control signal; and a channel one de-multiplexer having a data input, a control input, and first and second outputs, the channel one de-multiplexer operative to separate channel one decoded data into channel one primary data and channel one side channel data, the data input receiving channel one decoded data from the channel one decoder, the control input receiving the DEI signal from the DEI signal and FIFO control signal recovery logic, the first output producing channel one side channel data, and the second output producing channel one primary data.
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18. A high-speed digital transmitter capable of sending side channel data, the transmitter comprising:
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a channel zero encoder means for producing channel zero encoded data, said channel zero encoder means having first and second inputs and an output, the first input receiving channel zero primary data, the second input receiving a channel zero DEout signal, and the output producing channel zero encoded data based at least in part on the channel zero primary data and the channel zero DEout signal; a channel one multiplexing means for multiplexing channel one primary data and channel one side channel data, said channel one multiplexing means having first and second data inputs, a control input, and an output, the first data input receiving channel one primary data, the second data input receiving channel one side channel data, the control input receiving a DEI signal, and the output providing channel one side channel data or channel one primary data depending on the value of the DEI signal; a channel one DEout control logic means for producing a channel one DEout signal for facilitating transfer of channel one side channel data, said channel one DEout control logic means having an input and an output, the first input receiving a DEI signal, and the output producing a channel one DEout signal; and a channel one encoding means for producing channel one encoded data, said channel one encoding means having first and second inputs and an output, the first input receiving the output of the channel one multiplexer, the second input receiving the output of the channel one DEout control logic, the output producing channel one encoded data based at least in part on the two inputs. - View Dependent Claims (19, 20)
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21. A high-speed digital receiver capable of receiving side channel data, the receiver comprising:
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a channel zero decoder means for producing channel zero decoder data and a channel zero DEout signal, said channel zero decoder means having an input and first and second outputs, the first input receiving channel zero encoded data, the first output producing a channel zero decoded data signal the second output producing a channel zero DEout signal; a channel one decoder means for producing channel one decoded data and a channel one DEout signal, said channel one decoder means having at least one input and at least first and second outputs, the first input receiving channel one encoded data, the first output producing channel one decoded data, the second output producing a channel one DEout signal; DEI signal and FIFO control signal recovery logic means for deriving a DEI signal, said DEI signal and FIFO control signal recovery logic means having first and second inputs and first and second outputs, the first input receiving the channel zero DEout signal, the second input receiving the channel one DEout signal, the first output producing a DEI signal, the second output producing a first FIFO control signal, and a de-multiplexing means for separating a data signal into channel one primary data and channel one side channel data, said de-multiplexing means having a data input, a control input, and first and second outputs, the data input receiving channel one decoded data from the channel one decoder, the control input receiving the DEI signal from the DEI signal and FIFO control signal recovery logic, the first output producing channel one side channel data, and the second output producing channel one primary data.
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22. A method or sending side channel data over a communication link having a transmitter, a receiver, and at least a channel zero and a channel one connecting the transmitter and the receiver, the method comprising:
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encoding channel zero primary data, and DEI data for transmission on channel zero; deriving a channel one DEout signal using channel one DEout control logic having an input and an output, a first input receiving a DEI signal, and the output producing a channel one DEout signal for facilitating transfer of channel one side channel data; encoding channel one primary data channel one side channel data, and DEout signal data for transmission on channel one. - View Dependent Claims (23, 24, 25)
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26. A high-speed digital transmitter capable of sending side channel data, the transmitter comprising:
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a channel zero encoder having first, second, third and fourth inputs and an output, the first input receiving channel zero primary data, the second input receiving a DEI signal, the third input receiving an Hsync signal, the fourth input receiving a Vsync signal, and the output producing channel zero encoded data, the channel zero encoder operative to produce channel zero encoded data based at least in part on the channel zero primary data, the DEI signal, the Hsync signal, and the Vsync signal; a channel one FIFO having an input for receiving channel one side channel data and an output for providing channel one side channel data; a channel one multiplexer having at least first and second data inputs, at least one control input, and at least one output, the channel one multiplexer operative to multiplex channel one primary data and channel one side channel data, the first data input receiving channel one primary data, the second data input coupled to the output of the channel one FIFO for receiving channel one side channel data, the control input receiving a DEI signal, and the output providing a multiplexed signal including channel one side channel data and channel one primary data; channel one DEout control logic having a first input and an output, channel one DEout control logic operative to produce a channel one DEout signal for facilitating transfer of channel one side channel data, the first input receiving a DEI signal, and the output producing a channel one DEout signal; and a channel one encoder having first and second inputs and an output, the first input receiving the output of the channel one multiplexer, the second input receiving the output of the channel one DEout control logic, the output producing channel one encoded data, the channel one encoder operative to produce channel one encoded data based at least in part on the first and second inputs.
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27. A high-speed digital receiver capable of receiving side channel data, the receiver comprising:
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a channel zero decoder having a first input and first and second outputs, the first input receiving channel zero encoded data, the first output producing a channel zero decoded data signal, the second output producing a channel zero DEout signal, the channel zero decoder operative to produce channel zero decoded data and a channel zero DEout signal from the channel zero encoded data; a channel one decoder having at least an input and first and second outputs, the first input receiving channel one encoded data, the first output producing channel one decoded data, the second output producing a channel one DEout signal, the channel one decoder operative to produce channel one decoded data and a channel one DEout signal from the channel one encoded data; a DEI signal and a FIFO control signal recovery logic having first and second inputs and first and second outputs, the first input receiving the channel zero DEout signal, the second input receiving the channel one DEout signal, the DEI signal and FIFO control signal recovery logic operative to derive a DEI signal, the first output producing a DEI signal, the second output producing a first FIFO control signal, wherein the DEI signal and FIFO control signal recovery logic comprises; a first AND gate having first, second and third inputs and an output, the first input adapted to receive the channel zero DEout signal from the channel zero decoder, the second input adapted to receive the channel one DEout signal from the channel one decoder, the third input adapted to receive the channel two DEout signal from the channel two decoder, the output providing the DEI signal; an inverter having an input and an output, the input coupled to the output of the first AND gate to receive the DEI signal, the output providing an inverted DEI signal; a second AND gate having first and second inputs and an output, the first input coupled to the output of the inverter to receive the inverted DEI signal, the second input adapted to receive the channel one DEout signal from the channel one decoder, the output providing a channel one FIFO control signal; and a third AND gate having first and second inputs and an output, the first input coupled to the output of the inverter to receive the inverted DEI signal, the second input adapted to receive the channel two DEout signal from the channel two decoder, the output providing a channel two FIFO control signal, and a channel one de-multiplexer having a data input, a control input, and first and second outputs, the channel one de-multiplexer operative to separate channel one decoded data into channel one primary data and channel one side channel data, the data input receiving channel one decoded data from the channel one decoder, the control input receiving the DEI signal from the DEI signal and FIFO control signal recovery logic, the first output producing channel one side channel data, and the second output producing channel one primary data.
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Specification