Interleaver for iterative decoder
First Claim
1. An interleaver memory structure for facilitating the decoding of a plurality of encoded symbols, the interleaver memory structure comprising:
- during a first clock cycle;
a first interleaver pattern memory receives a first sequential read address;
a second interleaver pattern memory receives a first sequential write address;
during a second clock cycle;
the first interleaver pattern memory receives a second sequential write address;
the second interleaver pattern memory receives a second sequential read address;
a first read address is received from the first interleaver pattern memory for use by a first interleaver memory;
a first write address is received from the second interleaver pattern memory for use by a second interleaver memory;
during a third clock cycle;
the first interleaver pattern memory receives a third sequential read address;
the second interleaver pattern memory receives a third sequential write address;
a second write address is received from the first interleaver pattern memory for use by the first interleaver memory;
a second read address is received from the second interleaver pattern memory for use by the second interleaver memory;
a first data is read from the first interleaver memory;
a second data is written to the second interleaver memory; and
wherein each of the first interleaver pattern memory, the second interleaver pattern memory, the first interleaver memory, and the second interleaver memory are implemented using single port memory structures.
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Accused Products
Abstract
Interleaver for iterative decoder. A memory management scheme allows for single plane/single port memory devices to be used by the interleaver. The design is adaptable to soft-in soft-out (SISO) decoders that perform iterative decoding. The interleaver may be implemented within communication devices that implement two distinct SISOs that operate cooperatively or within communication devices that employ a single SISO (in a recycled embodiment) that functionally performs the analogous decoding operations that would be performed by the two distinct SISO implementation. The use of single plane/single port memory devices by the interleaver allows for a great deal of savings from many perspectives: the sizes of the required interleaver memory and the interleaver pattern memory are both cut in half using this approach, and a cost savings may also be realized, in that, cheaper, slower memories may be used since each respective interleaver memory is read only every other cycle.
17 Citations
35 Claims
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1. An interleaver memory structure for facilitating the decoding of a plurality of encoded symbols, the interleaver memory structure comprising:
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during a first clock cycle;
a first interleaver pattern memory receives a first sequential read address;
a second interleaver pattern memory receives a first sequential write address;
during a second clock cycle;
the first interleaver pattern memory receives a second sequential write address;
the second interleaver pattern memory receives a second sequential read address;
a first read address is received from the first interleaver pattern memory for use by a first interleaver memory;
a first write address is received from the second interleaver pattern memory for use by a second interleaver memory;
during a third clock cycle;
the first interleaver pattern memory receives a third sequential read address;
the second interleaver pattern memory receives a third sequential write address;
a second write address is received from the first interleaver pattern memory for use by the first interleaver memory;
a second read address is received from the second interleaver pattern memory for use by the second interleaver memory;
a first data is read from the first interleaver memory;
a second data is written to the second interleaver memory; and
wherein each of the first interleaver pattern memory, the second interleaver pattern memory, the first interleaver memory, and the second interleaver memory are implemented using single port memory structures. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A soft-in soft-out (SISO) decoder that includes an interleaver memory structure for facilitating the decoding of a plurality of encoded symbols, the SISO decoder comprising:
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a top SISO that, based on a plurality of trellis metrics, calculates a first plurality of extrinsic values for each encoded symbol of the plurality of encoded symbols;
wherein the interleaver memory structure interleaves the first plurality of extrinsic values to generate a first “
a priori probability”
(app) information;
a bottom SISO that, based on the plurality of trellis metrics, calculates a second plurality of extrinsic values for each encoded symbol of the plurality of encoded symbols according to the respective rate control;
wherein the interleaver memory structure de-interleaves the second plurality of extrinsic values to generate a second “
a priori probability”
(app) information;
wherein the first “
a priori probability”
(app) information is fed back to the bottom SISO;
wherein the second “
a priori probability”
(app) information is fed back to the top SISO;
wherein the top SISO and the bottom SISO operate cooperatively to perform at least one iteration of iterative decoding to generate a plurality of soft symbol decisions, each soft symbol decision of the plurality of soft symbol decisions corresponds to an encoded symbol of the plurality of encoded symbols; and
an output processor, communicatively coupled to the bottom SISO, that generates a hard symbol decision for each soft symbol decision of the plurality of soft symbol decisions thereby making a best estimate for each encoded symbol of the plurality of encoded symbols;
wherein the interleaver memory structure includes a first interleaver pattern memory, a second interleaver pattern memory, a first interleaver memory, and a second interleaver memory that are all implemented using single port memory structures;
during a first clock cycle;
a first interleaver pattern memory receives a first sequential read address;
a second interleaver pattern memory receives a first sequential write address;
during a second clock cycle;
the first interleaver pattern memory receives a second sequential write address;
the second interleaver pattern memory receives a second sequential read address;
a first read address is received from the first interleaver pattern memory for use by a first interleaver memory;
a first write address is received from the second interleaver pattern memory for use by a second interleaver memory;
during a third clock cycle;
the first interleaver pattern memory receives a third sequential read address;
the second interleaver pattern memory receives a third sequential write address;
a second write address is received from the first interleaver pattern memory for use by the first interleaver memory;
a second read address is received from the second interleaver pattern memory for use by the second interleaver memory;
a first data is read from the first interleaver memory;
a second data is written to the second interleaver memory; and
wherein each of the first interleaver pattern memory, the second interleaver pattern memory, the first interleaver memory, and the second interleaver memory are implemented using single port memory structures. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. An interleaver memory processing method, the method comprising:
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during a first clock cycle;
providing a first sequential read address to a first interleaver pattern memory;
providing a first sequential write address to a second interleaver pattern memory;
during a second clock cycle;
providing a second sequential write address to the first interleaver pattern memory;
providing a second sequential read address to the second interleaver pattern memory;
receiving a first read address from the first interleaver pattern memory for use by a first interleaver memory;
receiving a first write address from the second interleaver pattern memory for use by a second interleaver memory;
during a third clock cycle;
providing a third sequential read address to the first interleaver pattern memory;
providing a third sequential write address to the second interleaver pattern memory;
receiving a second write address from the first interleaver pattern memory for use by the first interleaver memory;
receiving a second read address from the second interleaver pattern memory for use by the second interleaver memory;
reading a first data from the first interleaver memory; and
writing a second data to the second interleaver memory. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33, 34, 35)
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Specification