Method and apparatus for coding bits of data in parallel
First Claim
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1. An address generation apparatus for an interleaver in a wireless communication system, the apparatus comprising:
- a counter; and
a plurality of address generators each coupled to the counter, each of the plurality of address generators comprising;
a memory storage device coupled to the counter, storing a plurality of counter values with corresponding counter offset values; and
a second counter coupled to the memory storage device, adapted to add the counter offset value to a previously generated address.
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Abstract
A method and apparatus for encoding multiple bits in parallel wherein outputs are generated recursively. During each clock cycle, the encoder processes multiple bits and generates outputs consistent with those generated sequentially over multiple clock cycles in a conventional convolutional encoder. In one embodiment, input data is stored in multiple memory storage units, which are then each uniquely addressed to provide data to parallel encoders.
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8 Claims
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1. An address generation apparatus for an interleaver in a wireless communication system, the apparatus comprising:
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a counter; and
a plurality of address generators each coupled to the counter, each of the plurality of address generators comprising;
a memory storage device coupled to the counter, storing a plurality of counter values with corresponding counter offset values; and
a second counter coupled to the memory storage device, adapted to add the counter offset value to a previously generated address. - View Dependent Claims (2, 3, 4)
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5. A data encoder, comprising:
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a plurality of memories for storing sequential input information bits;
a plurality of interleavers for scrambling the input information bits, each of the plurality of interleavers configured to receive input information bits in parallel;
a first encoder coupled to a first of the memories, the first encoder adapted to encode the sequential input information bits; and
a second encoder coupled to the plurality of memories, the second encoder adapted to encode the interleaved input information bits. - View Dependent Claims (6, 7, 8)
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Specification