Deterministic hardware reset for FRC machine
First Claim
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1. An apparatus comprising:
- a functional redundancy checking (FRC) processor including;
first and second execution cores to operate in FRC mode;
first and second scan chain corresponding to the first and second execution cores to transfer data to one or more nodes of the first and second execution cores; and
a reset module including a pattern generator to store and provide an identical bit pattern to the first and second scan chains, responsive to a reset signal.
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Abstract
A processor includes one or more execution cores, each execution core having an associated scan chain to provide data to a set of voltage nodes of the core. A reset module drives a data pattern onto the scan line, responsive to a reset event. The data pattern places the set of voltage nodes of each execution core into specified logic states. For a processor including multiple execution cores configured to operate in an FRC mode, identical data patterns are driven onto the scan chains to reduce indeterminacy in the reset machine state of the processor.
36 Citations
37 Claims
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1. An apparatus comprising:
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a functional redundancy checking (FRC) processor including;
first and second execution cores to operate in FRC mode;
first and second scan chain corresponding to the first and second execution cores to transfer data to one or more nodes of the first and second execution cores; and
a reset module including a pattern generator to store and provide an identical bit pattern to the first and second scan chains, responsive to a reset signal. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method for resetting a multicore FRC processor comprising:
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detecting a reset event;
generating a bit pattern in a reset module of the multicore FRC processor;
applying the bit pattern to a corresponding scan chain in each of the execution cores of the processor, the bit pattern to drive specific states to one or more processor nodes accessible through the scan chains. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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14. A system comprising:
a processor including;
first and second execution cores to be operated an FRC mode, responsive to a mode bit, each of the execution cores including a scan chain to transfer data to a first set of nodes of the execution core;
an FRC checker to be activated in FRC mode to compare data from the first and second execution cores; and
a reset module to apply a bit pattern to the scan chains of the first and second execution cores, responsive to a reset event in the system. - View Dependent Claims (15, 16, 17, 18)
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19. An apparatus comprising:
a FRC processor including, a first and second execution core to operate in FRC mode, each having a first set of voltage nodes coupled through data and clock lines; and
a reset module, including a pattern generator to drive a data signal and a clock signal to the first sets of voltage nodes, responsive to occurrence of a reset event, the data signal to place the voltage nodes of the first sets in specified logic states. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26)
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27. A multicore processor comprising:
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a first and second execution core to operate in a functional redundancy checking (FRC) mode;
a first and second scan chains corresponding to the first and second execution cores to transfer data to one or more nodes of the first and second execution cores;
a FRC boundary checker to compare nodes of the first and second execution cores; and
an internal reset module, including a pattern generator to store bit pattern, to provide the bit pattern to the first and second scan chains to put the first and second execution cores into a deterministic state responsive to a reset signal generated upon detection of a mismatch by the FRC boundary checker. - View Dependent Claims (28, 29, 30, 31, 32)
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33. A method for resetting a functional redundancy checking (FRC processor comprising:
performing a deterministic hardware reset in the FRC processor, the performing including, performing functional redundancy boundary checking;
generating a reset event upon a functional redundancy boundary checking mismatch;
generating a bit pattern responsive to the reset event; and
driving the bit pattern into scan chains. - View Dependent Claims (34, 35, 36, 37)
Specification