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Deterministic hardware reset for FRC machine

  • US 6,954,886 B2
  • Filed: 12/31/2001
  • Issued: 10/11/2005
  • Est. Priority Date: 12/31/2001
  • Status: Expired due to Fees
First Claim
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1. An apparatus comprising:

  • a functional redundancy checking (FRC) processor including;

    first and second execution cores to operate in FRC mode;

    first and second scan chain corresponding to the first and second execution cores to transfer data to one or more nodes of the first and second execution cores; and

    a reset module including a pattern generator to store and provide an identical bit pattern to the first and second scan chains, responsive to a reset signal.

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