Arithmetic built-in self-test of multiple scan-based integrated circuits
First Claim
1. A method, comprising:
- storing microcode in non-volatile memory in an integrated circuit for causing an embedded processor in the integrated circuit to generate a plurality of pseudo-random test patterns to be used in testing of the integrated circuit;
storing microcode in the non-volatile memory for causing the embedded processor to move at least one of the plurality of pseudo-random test patterns to a test port register coupled to the embedded processor; and
storing microcode in the non-volatile memory for causing the embedded processor to move test responses from the test port register to the embedded processor.
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Abstract
An apparatus and method provide for an arithmetic built-in self test (ABIST) of a number of peripheral devices having parallel scan registers coupled to a processor core, all within an integrated circuit. Using the data paths of the processor core, operating logic generates pseudo-random test patterns for the peripheral devices, employing a mixed congruential generation scheme. In one embodiment, generating the pseudo-random test patterns includes multiplying n least significant bits of a 2n-bit pseudo-random number generated in an immediately preceding iteration and stored in a first register, with an n-bit multiplier constant stored in a second register to produce a 2n-bit product, adding the 2n-bit product to n most significant bits of the 2n-bit pseudo-random number stored in n least significant locations of an accumulator with 2n locations to produce a new 2n-bit pseudo-random number for a current iteration, and outputting n least significant bits of the new 2n-bit pseudo-random number as an n-bit pseudo-random test vector for the peripheral devices.
56 Citations
21 Claims
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1. A method, comprising:
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storing microcode in non-volatile memory in an integrated circuit for causing an embedded processor in the integrated circuit to generate a plurality of pseudo-random test patterns to be used in testing of the integrated circuit;
storing microcode in the non-volatile memory for causing the embedded processor to move at least one of the plurality of pseudo-random test patterns to a test port register coupled to the embedded processor; and
storing microcode in the non-volatile memory for causing the embedded processor to move test responses from the test port register to the embedded processor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. One or more computer-readable media having computer-executable instructions for performing a method comprising:
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storing microcode in non-volatile memory in an integrated circuit for causing an embedded processor in the integrated circuit to generate a plurality of pseudo-random test patterns to be used in testing of the integrated circuit;
storing microcode in the non-volatile memory for causing the embedded processor to move at least one of the plurality of pseudo-random test patterns to a test port register coupled to the embedded processor; and
storing microcode in the non-volatile memory for causing the embedded processor to move test responses from the test port register to the embedded processor.
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11. An apparatus, comprising:
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means for generating pseudo-random test patterns in an integrated circuit, wherein the integrated circuit comprises an embedded processor core and a plurality of peripheral devices, the embedded processor core comprising a plurality of data paths, and wherein the means for generating pseudo-random test patterns comprises multiplying n least significant bits of a 2n-bit pseudo-random number generated in an immediately preceding iteration and stored in a first register, with an n-bit multiplier constant stored in a second register to produce a 2n-bit product;
means for testing the plurality of peripheral devices using the pseudo-random test patterns and the plurality of data paths; and
means for compacting peripheral device test-response data. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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19. A method for testing integrated circuits, comprising:
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a step for producing at least one two-dimensional pseudo-random test pattern in an integrated circuit, the integrated circuit having an embedded processor and a peripheral device;
a step for generating at least one two-dimensional deterministic test pattern in the integrated circuit;
a step for testing the peripheral device using the two-dimensional pseudo-random test pattern and the two-dimensional deterministic test pattern; and
a step for compacting test-response data. - View Dependent Claims (20, 21)
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Specification