Recording classification of instructions executed by a computer

• US 6,954,923 B1
• Filed: 07/07/1999
• Issued: 10/11/2005
• Est. Priority Date: 01/28/1999
• Status: Expired due to Term

• Current Assignee: Advanced Silicon Technologies LLC
• Original Assignee: ATI International SRL (Advanced Micro Devices, Inc.)
• Inventors: Yates, Jr., John S., Reese, David L., Van Dyke, Korbin S.
• Primary Examiner(s): DAS, CHAMELI
• Application Number:
  US09/348,317
• Time in Patent Office: 2,288 Days
• Field of Search: 717127-131, 717/136, 717/140, 717/158, 717/159, 717/149, 717/153, 717/154, 711/100, 712/237, 712/239, 712/208, 712/220
• US Class Current: 717/130
• CPC Class Codes: G06F 9/30174 for non-native instruction set, e.g. Javabyte, legacy code
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/4486 Formation of subprogram jump address

Abstract

An instruction processor to execute two instruction sets. Instructions are stored in different virtual memory pages of a single address space, and are coded for computers of two different instruction sets, and use of two different calling conventions. The instruction processor interprets instructions under, alternately, the first or second instruction set as directed by a first flag stored in table entries corresponding to memory pages for the instructions. The processor recognizes when program execution has transferred from a page of instructions using the first data storage convention to a page of instructions using the second data storage convention, as indicated by a second flag stored in the table entries, and then adjusts a data storage content of the computer from the first storage convention to the second data storage convention. A history record provides a record of a classification of a recently-executed instruction.

Claims

1. A microprocessor and support software, comprising:

an instruction pipeline designed to execute instructions of an instruction set, control-transfer instructions of the instructions being instructions defined to transfer execution control of a computer from a source instruction to a destination instruction, control-flow instructions of the instruction set being classified into a relatively small plurality of classes relative to the number of instruction opcodes executable by the instruction pipeline, most divisions in the classification being based on a static encoding of control-flow instructions executed, with at most minor divisions in the classification being based on dynamic or data-dependent execution behavior;

a storage register designed to store, and updating circuitry active during execution of a program on the microprocessor, designed to record into the storage register, as part of the execution of control-flow instructions of the instruction set and without software intervention, a value reflecting the class, from among the encoding-based classification, of a control-flow instruction recently executed by the pipeline;

software programmed to adjust the storage contents of the computer to reestablish in the context of the destination instruction a context logically equivalent to the context of the computer at the time of the control transfer instruction, the adjustment being determined, at least in part, by a classification of the control-transfer instruction; and

invoking circuitry to invoke the software before executing the destination instruction of at least some of the control transfer instructions.

2. The microprocessor of claim 1, wherein:

at least three-quarters of the classification divisions are defined solely by static encoding of instructions executed;

at least some of the classification divisions are defined by the opcode of the instructions; and

at least some of the classification divisions are defined by immediate values of instructions.

3. The method of claim 1, wherein:

at least four of the classification divisions distinguish different classes of jump instructions emitted by a typical compiler for the computer primarily to effect intra-subprogram transfers; and

at least half of the classification divisions distinguish classes of control transfers that either (a) induce a context switch, (b) are emitted by a typical compiler for the computer primarily to effect a control transfer between subprograms, or (c) effect argument passing or return as a side effect of the control transfer.

4. The method of claim 1, wherein:

at least some of the immediate values defining the classification divisions are branch displacements; and

at least some of the immediate values defining the classification divisions are immediate values having no effect on the execution of the instructions in which they are encoded, except to update the storage register.

5. The method of claim 1, wherein at least some instructions of the computer are assigned to a classification division ignored by the circuitry, execution of instructions in this ignored classification leaving intact the previous contents of the storage register.

6. A method, comprising:

classifying control-flow instructions of a computer instruction set into a plurality of classes; and

during execution of a program on a computer, as part of the execution of instructions of the instruction set, updating a record of the class of the classified control-flow instruction most recently executed.

7. The method of claim 6, further comprising:

detecting when the computer'"'"'s execution flows from code observing a first data storage convention to code observing a second data storage convention, the record recording a class of instruction effecting the transitional execution flow; and

in response to the detecting, altering the data storage content of the computer to create a program context under the second data storage convention that is logically equivalent to a pre-alteration program context under the first data storage convention, the altering process being determined, at least in part, by the instruction classification record.

8. The method of claim 7, wherein:

one of the two data storage conventions is a register-based calling convention, and the other data storage convention is a memory stack-based calling convention.

9. The method of claim 8, wherein:

at least four of the classification divisions distinguish different classes of jump instructions emitted by a typical compiler for the computer primarily to effect intra-subprogram transfers; and

at least half of the classification divisions distinguish classes of control transfers that either (a) induce a context switch, (b) are emitted by a typical compiler for the computer primarily to effect a control transfer between subprograms, or (c) effect argument passing or return as a side effect of the control transfer.

10. The method of claim 8, wherein:

in some of the control-flow instructions, the classification is dynamically determined based on a full/empty status of a register.

11. The method of claim 6, wherein:

in some of the control-flow instructions, the classification is encoded as an immediate value of instructions, the immediate value having no effect on the execution of the instruction in which it is encoded, except to update the class record; and

in some of the control-flow instructions, the classification is statically determined by the opcode of the instructions.

12. The method of claim 6, wherein:

at least four of the classification divisions distinguish different classes of jump instructions emitted by a typical compiler for the computer primarily to effect intra-subprogram transfers; and

at least half of the classification divisions distinguish classes of control transfers that either (a) induce a context switch, (b) are emitted by a typical compiler for the computer primarily to effect a control transfer between subprograms, or (c) effect argument passing or return as a side effect of the control transfer.

13. The method of claim 6, wherein the execution of the program on the computer is performed in the hardware instruction pipeline of the computer.

14. A method, comprising:

executing a control-transfer instruction that transfers execution control of a computer from a first execution context to a destination instruction for execution in a second execution context;

before executing the destination instruction, reconfiguring the storage state of the computer to reestablish under the second execution context the logical state of the computer as interpreted under the first execution context;

the reconfiguring being determined, at least in part, by a classification of the control-transfer instruction.

15. The method of claim 14, wherein the destination instruction is an entry point to an off-the-shelf binary for an operating system coded in an instruction set non-native to the computer, the non-native instruction set providing access to a reduced subset of the resources of the computer.

16. The method of claim 14, wherein:

at least four of the classification divisions distinguish different classes of jump instructions emitted by a typical compiler for the computer primarily to effect intra-subprogram transfers; and

at least half of the classification divisions distinguish classes of control transfers that either (a) induce a context switch, (b) are emitted by a typical compiler for the computer primarily to effect a control transfer between subprograms, or (c) effect argument passing or return as a side effect of the control transfer.

17. The method of claim 14, wherein:

in some of the control-flow instructions, the classification is encoded as an immediate value of instructions, the immediate value having no effect on the execution of the instruction in which it is encoded, except to update the class record.

18. The method of claim 14, wherein:

in some of the control-flow instructions, the classification is statically determined by the opcode of the instructions; and

in other of the control-flow instructions, the classification is dynamically determined with reference to a state of a processor register and/or data register of the computer.

19. The method of claim 18, wherein:

for some of the control-flow instructions, the dynamic classification is determined based on a full/empty status of a register.

20. The method of claim 14:

wherein one of the two data storage conventions is a register-based calling convention, and the other data storage convention is a memory stack-based calling convention;

and further comprising;

detecting when the computer'"'"'s execution flows from code observing the register-based calling convention to code observing the memory stack-based calling convention, the record recording the classification of the instruction effecting the transitional execution flow; and

in response to the detecting, altering the data storage content of the computer to create a program context under the memory stack-based calling convention that is logically equivalent to a pre-alteration program context under the register-based calling convention the altering process being determined, at least in part, by the instruction classification record.

21. The method of claim 20, wherein:

at least four of the classification divisions distinguish different classes of jump instructions emitted by a typical compiler for the computer primarily to effect intra-subprogram transfers; and

at least half of the classification divisions distinguish classes of control transfers that either (a) induce a context switch, (b) are emitted by a typical compiler for the computer primarily to effect a control transfer between subprograms, or (c) effect argument passing or return as a side effect of the control transfer.

22. The method of claim 20, wherein:

in some of the control-flow instructions, the classification is encoded as an immediate value of the instructions, the immediate value having no effect on the execution of the instruction in which it is encoded, except to update the class record.

23. The method of claim 20, wherein:

in some of the control-flow instructions, the classification is statically determined by the opcode of the instructions; and

in other of the control-flow instructions, the classification is dynamically determined based on a full/empty status of a register.

24. The method of claim 20, wherein:

the rearranging is performed by an exception handler, the handler being selected by an exception vector based at least in part on the instruction classification record.

25. A microprocessor, comprising:

an instruction pipeline designed to execute instructions of an instruction set, the instructions of the instruction set being classified into a relatively small number of classes relative to the number of instruction opcodes executable by the instruction pipeline, most divisions in the classification being based on a static encoding of instructions executed, with at most minor divisions in the classification being based on dynamic or data-dependent execution behavior;

a storage register designed to store, and circuitry designed to record without software intervention into the storage register, a value reflecting the class, from among the encoding-based classification, of an instruction recently executed by the pipeline.

26. The microprocessor of claim 25, wherein at least three-quarters of the classification divisions are defined solely by static encoding of instructions executed.

27. The microprocessor of claim 26, wherein:

some of the classification divisions are defined by the opcode of the instructions; and

some of the classification divisions are defined by immediate values of instructions.

28. The microprocessor of claim 27, wherein:

at least four of the classification divisions distinguish different classes of jump instructions emitted by a typical compiler for the computer primarily to effect intra-subprogram transfers; and

at least half of the classification divisions distinguish classes of control transfers that either (a) induce a context switch, (b) are emitted by a typical compiler for the computer primarily to effect a control transfer between subprograms, or (c) effect argument passing or return as a side effect of the control transfer.

29. The microprocessor of claim 27, wherein at least some of the immediate values defining the classification divisions are branch displacements.

30. The microprocessor of claim 27, wherein at least some of the immediate values defining the classification divisions are immediate values having no effect on the execution of the instructions in which they are encoded, except to update the storage register.

31. The microprocessor of claim 25, wherein:

at least some of the classification divisions are determined by dynamic reference to a state of architecturally-visible processor registers and/or general purpose registers of the computer.

32. The microprocessor of claim 31, wherein the state of the register is a state maintained distinct from a data content of the register.

33. The microprocessor of claim 25, wherein at least some instructions of the computer are assigned to a classification division ignored by the circuitry, execution of instructions in this ignored classification leaving intact the previous contents of the storage register.

34. The microprocessor of claim 25, wherein the number of classes is at most 32.

35. The microprocessor of claim 25, further comprising hardware or software designed to use the content of the storage register to annotate a descriptor in a profile of the execution of a program running on the microprocessor.