Carbon nanotube memory cell for integrated circuit structure with removable side spacers to permit access to memory cell and process for forming such memory cell

• US 6,955,937 B1
• Filed: 08/12/2004
• Issued: 10/18/2005
• Est. Priority Date: 08/12/2004
• Status: Expired due to Fees

• Current Assignee: Nantero Incorporated
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Burke, Peter A., Sun, Sey-Shing, Lu, Hong-Qiang
• Primary Examiner(s): Gurley, Lynne A.
• Assistant Examiner(s): STEVENSON, ANDRE C
• Application Number:
  US10/917,551
• Time in Patent Office: 432 Days
• Field of Search: 438/53, 438/216, 438/67, 438/156, 438/175, 438/209, 438/99, 257/296, 257/17, 257/213, 257/288, 257/40, 257/306, 257/309, 257/531
• US Class Current: 438/53
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 13/025 using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
• CPC Class Codes: G11C 2213/16 Memory cell being a nanotube, e.g. suspended nanotube
• CPC Class Codes: H01L 27/10 including a plurality of individual components in a repetitive configuration
• CPC Class Codes: Y10S 977/943 Information storage or retrieval using nanostructure

Abstract

A carbon nanotube memory cell for an integrated circuit wherein a chamber is constructed in a layer of a dielectric material such as silicon nitride down to a first electrical contact. This chamber is filled with polysilicon. A layer of a carbon nanotube mat or ribbon is formed over the silicon nitride layer and the chamber. A dielectric material, such as an oxide layer, is formed over the nanotube strips and patterned to form an upper chamber down to the ribbon layer to permit the ribbon to move into the upper chamber or into the lower chamber. The upper chamber is then filled with polysilicon. A silicon nitride layer is formed over the oxide layer and a contact opening is formed down to the ribbon and filled with tungsten that is then patterned to form metal lines. Any exposed silicon nitride is removed. A polysilicon layer is formed over the tungsten lines and anisotropically etched to remove polysilicon on the horizontal surfaces but leave polysilicon sidewall spacers. A silicon oxide layer is deposited over the structure and also anisotropically etched forming silicon oxide sidewall spacers on the polysilicon sidewall spacers. The polysilicon is wet etched with an etchant selective to adjacent materials to remove the polysilicon sidewalls spacers and all of the polysilicon in the chambers. Silicon oxide is formed over the structure and into the upper portion of the openings to seal the now empty chambers. A passivation layer may then be formed.

Claims

1. A process for making a carbon nanotube memory cell for an integrated circuit structure which comprises:

a) forming a first dielectric layer over a substrate;

b) forming a first metal layer over said first dielectric layer;

c) forming a second dielectric layer over said first metal layer;

d) patterning said second dielectric layer to form an opening in said second dielectric layer down to said first metal layer, said opening comprising a first chamber in said second dielectric layer;

e) filling said first chamber with a first removable material;

f) forming a porous carbon nanotube ribbon layer over said second dielectric layer and said first removable material—

filled first chamber therein;

g) forming a third layer of dielectric material over said carbon nanotube ribbon layer;

h) patterning said third dielectric layer to form an opening in said third dielectric layer down to said underlying carbon nanotube ribbon layer in registry with said first chamber formed in said second dielectric layer, whereby said opening in said third dielectric layer will function as an upper chamber for said memory cell in registry with said first chamber;

i) filling said upper chamber with a second removable material;

j) forming a fourth dielectric layer over the third dielectric layer and said second removable material-filled upper chamber therein;

k) forming a contact opening in said third and fourth dielectric layers down to said porous carbon nanotube ribbon;

l) forming a layer of conductive material over said fourth dielectric layer which fills said contact opening;

m) patterning said layer of conductive material and said fourth dielectric layer thereunder to form at least one line of said conductive material over said contact opening and said filled upper chamber, the width of said line over said filled chamber being less than the width of said filled—

upper chamber;

n) forming a layer of a third removable material over said structure;

o) anisotropically etching said layer of said third removable material to form first sidewall spacers of said third removable material on the sidewalls of said lines of conductive material;

p) forming a further dielectric layer over said structure;

q) anisotropically etching said further dielectric layer to form second sidewall spacers of said further dielectric material on the sidewalls of said first sidewall spacers of said third removable material;

r) removing said first sidewall spacers of said third removable material to provide an opening to said filled upper chamber;

s) removing said first and second material respectively in said lower and upper chambers through said opening formed by removal of said first sidewall spacers; and

t) forming a dielectric layer over said structure to seal the opening leading to said upper and lower chambers.

2. The process for forming a carbon nanotube ribbon memory cell of claim 1 wherein said step of forming said first dielectric layer on a substrate further comprises forming said first dielectric layer over a silicon wafer.

3. The process for forming a carbon nanotube ribbon memory cell of claim 1 wherein said step of forming a first dielectric layer over a substrate further comprises the step of forming a first silicon oxide (SiO₂) layer over said substrate.

4. The process for forming a carbon nanotube ribbon memory cell of claim 1 wherein said step of forming a first metal layer comprises forming a main metal layer selected from the group consisting of tungsten, titanium, titanium nitride, tantalum, tantalum nitride, and aluminum.

5. The process for forming a porous carbon nanotube ribbon memory cell of claim 4 wherein said step of forming said first main metal layer further includes forming at least one electrically conductive liner layer formed over said first dielectric layer and beneath said main metal layer.

6. The process for forming a carbon nanotube ribbon memory cell of claim 5 wherein said step of forming said first main metal layer further comprises patterning said first main metal layer to form metal lines.

7. The process for forming a carbon nanotube ribbon memory cell of claim 3 wherein said step of forming a second dielectric layer further comprises forming over said first metal layer a silicon nitride dielectric layer having a thickness ranging from about 8 nm to about 30 nm.

8. The process for forming a carbon nanotube ribbon memory cell of claim 1 wherein said step of filling said first chamber with a first removable material comprises further comprises filling said first chamber with a first removable material capable of being selectively removed with a wet etch.

9. The process for forming a carbon nanotube ribbon memory cell of claim 8 wherein said step of filling said first chamber with a first removable material capable of being selectively removed with a wet etch further comprises filling said first chamber with silicon.

10. The process for forming a carbon nanotube ribbon memory cell of claim 1 including the further step of patterning said porous carbon nanotube ribbon to form strips.

11. The process for forming a carbon nanotube ribbon memory cell of claim 1 wherein said step of forming a third dielectric layer over said carbon nanotube ribbon layer further comprises forming a silicon oxide (SiO₂) layer over said carbon nanotube ribbon layer.

12. The process for forming a carbon nanotube ribbon memory cell of claim 11 wherein said step of forming a third dielectric layer further comprises forming over said carbon nanotube ribbon a silicon oxide (SiO₂) dielectric layer having a thickness ranging from about 8 nm to about 30 nm.

13. The process for forming a carbon nanotube ribbon memory cell of claim 1 wherein said step of filling said second chamber with a second removable material further comprises filling said second chamber with a material capable of being selectively removed with a wet etch.

14. The process for forming a carbon nanotube ribbon memory cell of claim 13 wherein said step of filling said second chamber with a second removable material capable of being selectively removed with a wet etch further comprises filling said second chamber with silicon.

15. The process for forming a carbon nanotube ribbon memory cell of claim 13 wherein said step of forming a fourth layer of dielectric material further comprises forming a layer of silicon nitride over said third layer of dielectric material.

16. The process for forming a carbon nanotube ribbon memory cell of claim 15 wherein said step of filling said upper chamber with a removable material comprises further comprises filling said upper chamber with a second removable material capable of being selectively removed with a wet etch.

17. The process for forming a carbon nanotube ribbon memory cell of claim 16 wherein said step of filling said upper chamber with a second removable material capable of being selectively removed with a wet etch further comprises filling said upper chamber with silicon.

18. The process for forming a carbon nanotube ribbon memory cell of claim 16 wherein said steps of filling said lower chamber with a first removable material, capable of being selectively removed with a wet etch, and said upper chamber with a second removable material capable of being selectively removed with a wet etch further comprises filling both said lower chamber and said upper chamber with the same removable material.

19. The process for forming a carbon nanotube ribbon memory cell of claim 15 wherein said step of forming a layer of conductive material which fills said contact opening further comprises filling said contact opening with tungsten.

20. In the formation of a carbon nanotube memory cell wherein a lower chamber is formed below a layer of carbon nanotubes, and an upper chamber is formed above said layer of carbon nanotubes, and in registry with said lower chamber, and both of said chambers are filled with a first removable material, the improvement which comprises:

a) forming an electrode above said filled upper chamber, said electrode having a width less than the width of said upper chamber and generally in registry with said upper chamber;

b) forming a layer of a second removable material over said structure, including said electrode;

c) anisotropically etching said layer of said second removable material to form first sidewall spacers of said second removable material on the sidewalls of said electrode;

d) forming over the resultant structure a layer of a material different from said second removable material;

e) anisotropically etching said layer of a different material to form second sidewall spacers of said different material on the sidewalls of said first sidewall spacers;

f) removing said first sidewall spacers of said second removable material to form one or more openings to said upper chamber;

g) removing said first removable material from said upper chamber and said lower chamber through said openings formed by removal of said first sidewall spacers of said second removable material; and

h) sealing said chambers after removal of all of said first removable material from said chambers.

21. In a carbon nanotube memory cell wherein a lower chamber is formed below a layer of carbon nanotubes, and an upper chamber is formed above said layer of carbon nanotubes, and in registry with said lower chamber, and both of said chambers have been previously filled with a removable filler material, the improvement which comprises:

a) an electrode formed above said upper chamber, said electrode having a width less than the width of said upper chamber and generally in registry with said upper chamber;

b) first sidewall spacers adjacent, but spaced from, the sidewalls of said electrode, and formed by

i) forming a layer of a removable material over said structure, including said electrode;

ii) anisotropically etching said layer of said removable material to form second sidewall spacers of said removable material on the sidewalls of said electrode;

iii) forming over the resultant structure a layer of a material different from said removable material;

iv) anisotropically etching said layer of a different material to form said first sidewall spacers on the sidewalls of said second spacers and spaced from the sidewalls of said electrode; and

v) removing said second sidewall spacers of said removable material;

c) one or more openings to said upper chamber formed by removal of said second sidewall spacers through which said removable filler material has been removed from said upper chamber and said lower chamber; and

d) sealing materials formed above said chambers after said removal of all of said filler material from said chambers.