Structure and method for latchup suppression utilizing trench and masked sub-collector implantation

• US 6,956,266 B1
• Filed: 09/09/2004
• Issued: 10/18/2005
• Est. Priority Date: 09/09/2004
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Voldman, Steven H., Watson, Anne E.
• Primary Examiner(s): Lebentritt, Michael
• Assistant Examiner(s): LINDSAY JR, WALTER LEE
• Application Number:
  US10/711,300
• Time in Patent Office: 404 Days
• Field of Search: 257/371, 257/372, 257/347, 257/336, 257/344, 257/330, 257/332
• US Class Current: 257/371
• CPC Class Codes: H01L 21/76237 introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0921 Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A method and structure for an integrated circuit comprising a substrate of a first polarity; a trench structure in the substrate; a well region of a second polarity abutting the trench structure; and a heavily doped region of the second polarity abutting the trench structure, wherein the heavily doped region is adapted to suppress latch-up in the integrated circuit, wherein the heavily doped region comprises a sub-collector region, and wherein the trench structure comprises a deep trench structure or a trench isolation structure. The integrated circuit further comprises a p+ anode in the well region and a n+ cathode in the well region, wherein the integrated circuit is configured as a latchup robust p-n diode. In another embodiment, the integrated circuit further comprises a p+ anode in the well region; a n+ cathode in the well region; and a gate structure over the p+ anode and n+ cathode.

Claims

1. An integrated circuit comprising:

a substrate of a first polarity;

a trench structure in said substrate;

a well region of a second polarity abutting said trench structure;

a heavily doped region of said second polarity abutting said trench structure; and

a shallow trench isolation region, wherein said trench structure comprises a deep trench structure having a depth and a width, wherein said depth is at least twice as large as said width, and wherein said shallow trench isolation region is over said deep trench structure,

wherein said heavily doped region having a dopant concentration greater than a dopant concentration of said well region, and wherein said heavily doped region is adapted to suppress latch-up in said integrated circuit.

2. The integrated circuit of claim 1, wherein said heavily doped region comprises a sub-collector region.

3. The integrated circuit of claim 1, wherein an aspect ratio of said depth to said width is at least 2.85.

4. The integrated circuit of claim 1, further comprising a shallow trench isolation region, wherein said trench structure comprises a trench isolation region having a depth and a width, wherein said depth is at least twice as large as said width, and wherein said trench isolation region traverses said shallow trench isolation region.

5. The integrated circuit of claim 4, wherein an aspect ratio of said depth to said width is at least 2.5.

6. The integrated circuit of claim 1, further comprising:

a p+ anode in said well region;

a n+ cathode in said well region; and

a gate structure over said p+ anode and said n+ cathode.

8. The CMOS device of claim 6, wherein said n-type sub-collector comprises a uniform dopant layer.

9. The CMOS device of claim 6, wherein said n-type sub-collector comprises a discontinuous dopant layer.

10. The CMOS device claim 6, wherein said n-type sub-collector is adjacent to a lower surface of said n-type retrograde well.

11. The CMOS device of claim 6, wherein said deep trench isolation region comprises a depth and a width, wherein said depth is at least twice as large as said width, and wherein said shallow trench isolation regions are over said deep trench isolation region.

7. A complementary metal oxide semiconductor (CMOS) device, said CMOS device comprising:

a p-type substrate;

shallow trench isolation (STI) regions in said p-type substrate;

p-type diffusion regions in said p-type substrate and in between successive ones of said STI regions;

a n-type retrograde well in said p-type substrate;

a deep trench isolation region bounding said p-type diffusion regions and said n-type retrograde well; and

a n-type sub-collector adjacent to a sidewall of said deep trench isolation region and below said STI regions,

wherein said p-type diffusion regions, said n-type retrograde well, and said p-type substrate form pnp parasitic bipolar transistor in said CMOS device, and

wherein said deep trench isolation region and said n-type sub-collector are adapted to suppress latch-tip in said CMOS device that is caused by said pnp parasitic bipolar transistor.