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Structure and method for latchup suppression utilizing trench and masked sub-collector implantation

  • US 6,956,266 B1
  • Filed: 09/09/2004
  • Issued: 10/18/2005
  • Est. Priority Date: 09/09/2004
  • Status: Expired due to Fees
First Claim
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1. An integrated circuit comprising:

  • a substrate of a first polarity;

    a trench structure in said substrate;

    a well region of a second polarity abutting said trench structure;

    a heavily doped region of said second polarity abutting said trench structure; and

    a shallow trench isolation region, wherein said trench structure comprises a deep trench structure having a depth and a width, wherein said depth is at least twice as large as said width, and wherein said shallow trench isolation region is over said deep trench structure,wherein said heavily doped region having a dopant concentration greater than a dopant concentration of said well region, and wherein said heavily doped region is adapted to suppress latch-up in said integrated circuit.

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