Constant RONswitch circuit with low distortion and reduction of pedestal errors

• US 6,956,411 B1
• Filed: 03/27/2003
• Issued: 10/18/2005
• Est. Priority Date: 03/27/2003
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Holloway, Peter R.
• Primary Examiner(s): Lam, Tuan T.
• Assistant Examiner(s): Nguyen, Hiep
• Application Number:
  US10/402,080
• Time in Patent Office: 936 Days
• Field of Search: 327/390, 327/391, 327/308, 327/389, 327/337, 327/374, 327/375, 327/94, 327/404, 327/384, 327/386
• US Class Current: 327/94
• CPC Class Codes: G11C 27/02 Sample-and-hold arrangements G11C27/04 takes precedence
• CPC Class Codes: G11C 27/024 using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: H03K 17/063 in field-effect transistor switches

Abstract

A low distortion, high frequency switch circuit for selectively coupling an input voltage terminal to an output voltage terminal includes a switching device coupled to the input voltage terminal and the output voltage terminal, a charge storage device, and a first, second and third switches. While the switch circuit is turned off, the charge storage device, typically a capacitor, is charged to a precharge voltage. Then, when the switch circuit is to be turned on, the charge storage device is coupled between the control terminal of the switching device and the input voltage terminal. As a result, the switching device receives a constant gate-to-source voltage approximately equals to the precharge voltage and becomes conductive with a minimum and constant R_ON for all values of input voltages. In another embodiment, the switch circuit includes a pedestal voltage compensation circuit for reducing charge injection induced pedestal errors.

Claims

1. A switch circuit for selectively coupling an input terminal to an output terminal comprising:

a switching device coupled between said input terminal and said output terminal, said switching device having a control terminal;

a charge storage device having a first terminal, and a second terminal;

a first switch coupled to said control terminal of said switching device, said first switch having a first position coupled to a first supply voltage and a second position being an open circuit;

a second switch coupled to said first terminal of said charge storage device, said second switch having a first position coupled to a second supply voltage and a second position coupled to said control terminal of said switching device; and

a third switch coupled to said second terminal of said charge storage device, said third switch having a first position coupled to said first supply voltage and a second position coupled to said input terminal;

wherein said first, second and third switches are in said first positions for turning off said switch circuit in response to a first clock signal, and said first, second and third switches are in said second positions for turning on said switch circuit in response to a second clock signal; and

wherein said first and second switches are coupled to said first positions responsive to said first clock signal a predetermined delay time after said second and third switches are disconnected from said second positions responsive to said second clock signals.

2. The switch circuit of claim 1, wherein said second and third switches are coupled to said second positions responsive to said second clock signal a predetermined delay time after said first and second switches are disconnected from said first positions responsive to said first clock signals.

3. The switch circuit of claim 1, wherein said switching device electrically connects said input terminal of said switch circuit to said output terminal when said first, second and third switches are in said second positions.

4. The switch circuit of claim 1, wherein said charge storage device is charged to a voltage value being the difference between said second supply voltage and said first supply voltage when said second and third switches are in said first positions.

5. The switch circuit of claim 1, wherein said first supply voltage is a ground voltage.

6. The switch circuit of claim 5, wherein said charge storage device is charged to said second supply voltage when said second and third switches are in said first positions.

7. The switch circuit of claim 6, wherein said second supply voltage is a power supply voltage of said switch circuit.

8. The switch circuit of claim 6, wherein said second supply voltage is a voltage less than a power supply voltage of said switch circuit.

9. The switch circuit of claim 6, wherein said second supply voltage is a voltage exceeding a power supply voltage of said switch circuit.

10. The switch circuit of claim 1, wherein said charge storage device comprises a capacitor.

11. The switch circuit of claim 10, wherein said charge storage device comprises a MOS capacitor.

12. The switch circuit of claim 10, wherein said charge storage device comprises an oxide capacitor.

13. The switch circuit of claim 10, wherein said charge storage device comprises a polysilicon-dielectric-polysilicon capacitor.

14. The switch circuit of claim 1, wherein a resistance between said input terminal and said output terminal of said switch circuit is substantially constant when said first, second and third switches are in said second positions.

15. The switch circuit of claim 1, wherein said switching device comprises a first NMOS transistor having a first current handling terminal coupled to said input terminal, a second current handling terminal coupled to said output terminal, and a gate terminal being said control terminal of said switching device.

16. The switch circuit of claim 15, wherein said first switch comprises a second NMOS transistor having a first current handling terminal coupled to said gate terminal of said first NMOS transistor, a second current handling terminal coupled to said first supply voltage, and a gate terminal driven by said first clock signal.

17. The switch circuit of claim 15, wherein said first switch comprises a second NMOS transistor and a third NMOS transistor connected in series, said second NMOS transistor having a first current handling terminal coupled to said gate terminal of said first NMOS transistor, a second current handling terminal coupled to a first current handling terminal of said third NMOS transistor, and a gate terminal coupled to a power supply voltage Vdd of said switch circuit;

and said third NMOS transistor having a second current handling terminal coupled to said first supply voltage, and a gate terminal driven by said first clock signal.

18. The switch circuit of claim 15, wherein said second switch comprises a first PMOS transistor having a first current handling terminal coupled to said second supply voltage, a second current handling terminal coupled to said first terminal of said charge storage device, and a gate terminal connected to said gate terminal of said first NMOS transistor.

19. The switch circuit of claim 18, wherein said second switch further comprises a second PMOS transistor having a first current handling terminal coupled to said gate terminal of said first NMOS transistor, a second current handling terminal coupled to first terminal of said charge storage device, and a gate terminal driven by a signal corresponding to said second clock signal.

20. The switch circuit of claim 19, wherein said signal corresponding to said second clock sigal is an inverse of said second clock signal.

21. The switch circuit of claim 18, wherein said second switch further comprises a second PMOS transistor having a first current handling terminal coupled to said gate terminal of said first NMOS transistor, a second current handling terminal coupled to first terminal of said charge storage device, and a gate terminal driven by said first clock signal, whereby said switch circuit is be turned on and off in response to said first clock signal only.

22. The switch circuit of claim 19 wherein said first and second PMOS transistors are placed in an N well, said N well being electrically coupled to said first terminal of said charge storage device.

23. The switch circuit of claim 22, wherein said charge storage device comprises a MOS capacitor implemented using a third PMOS transistor, said third PMOS transistor being placed in said N well.

24. The switch circuit of claim 19, wherein said first and second PMOS transistors are placed in a first N well and a second N well respectively, each of said first and second N wells being electrically coupled to said first terminal of said charge storage device.

25. The switch circuit of claim 24, wherein said charge storage device is a MOS capacitor implemented using a third PMOS transistor, said third PMOS transistor being placed in a third N well, said third N well being electrically coupled to said first terminal of said charge storage device.

26. The switch circuit of claim 22, wherein said second supply voltage is a power supply voltage of said switch circuit.

27. The switch circuit of claim 24, wherein said second supply voltage is a power supply voltage of said switch circuit.

28. The switch circuit of claim 19, wherein said first and second PMOS transistors have a maximum operating voltage and said second supply voltage is a voltage being a difference between said maximum operating voltage and a power supply voltage of said switch circuit.

29. The switch circuit of claim 19, wherein said switch circuit is manufactured using a dual-voltage fabrication process and said first and second PMOS transistors are high-voltage PMOS transistors.

30. The switch circuit of claim 15, wherein said switch circuit is manufactured using a dual-voltage fabrication process;

and said second switch comprises;

a first high-voltage NMOS transistor having a first current handling terminal coupled to said second supply voltage, a second current handling terminal coupled to said first terminal of said charge storage device, and a gate terminal connected to a voltage signal corresponding to a voltage signal at said gate terminal of said first NMOS transistor; and

a second high-voltage NMOS transistor having a first current handling terminal coupled to said gate terminal of said first NMOS transistor, a second current handling terminal coupled to first terminal of said charge storage device, and a gate terminal driven by said second clock signal.

31. The switch circuit of claim 15, wherein said third switch comprises a third NMOS transistor having a first current handling terminal coupled to said second terminal of said charge storage device, a second current handling terminal coupled to said first supply voltage, and a gate terminal driven by said first clock signal.

32. The switch circuit of claim 31, wherein said third switch further comprises a fourth NMOS transistor having a first current handling terminal coupled to said input terminal, a second current handling terminal coupled to said first current handling terminal of said third NMOS transistor, and a gate terminal driven by said second clock signal.

33. The switch circuit of claim 32, wherein said third switch further comprises a third PMOS transistor having a first current handling terminal coupled to said input terminal, a second current handling terminal coupled to said first current handling terminal of said third NMOS transistor, and a gate terminal driven by a signal corresponding to said second clock signal.

34. The switch circuit of claim 33, wherein said signal corresponding to said second clock signal is an inverse of said second clock signal.

35. The switch circuit of claim 31, wherein said third switch further comprises a fifth NMOS transistor having a first current handling terminal coupled to said input terminal, a second current handling terminal coupled to said first current handling terminal of said third NMOS transistor, and a gate terminal coupled to said gate terminal of said first NMOS transistor.

36. The switch circuit of claim 1, wherein said switching device comprises a first PMOS transistor having a first current handling terminal coupled to said input terminal, a second current handling terminal coupled to said output terminal, and a gate terminal being said control terminal of said switching device.

37. The switch circuit of claim 36, wherein said first supply voltage is a power supply voltage of said switch circuit and said second supply voltage is a ground voltage.

39. The switch circuit of claim 1, further comprising:

a fourth switch coupled between said first position of said first switch and said first supply voltage, said fourth switch having a first position being an open circuit and a second position coupling said first position of said first switch to said first supply voltage; and

a capacitor divider circuit coupled between said output terminal and said first supply voltage, a common node of said capacitor divider circuit being coupled to said first position of said first switch;

wherein said fourth switch operates in response to said first clock signal and is in said first position when said switch circuit is turned off; and

said capacitor divider circuit generates a compensating charge at said output terminal, said compensating charge being derived from a channel charge originated from said control terminal of said switching device when said switch circuit is turned off.

40. The switch circuit of claim 39, wherein said fourth switch comprises a first NMOS transistor having a first current handling terminal coupled to said first position of said first switch, a second current handling terminal coupled to said first supply voltage, and a gate terminal driven by an inverse of said first clock signal.

41. The switch circuit of claim 39, wherein said capacitor divider circuit comprises a first capacitor and a second capacitor having equal capacitance.

42. The switch circuit of claim 16, further comprising:

a third NMOS transistor having a first current handling terminal coupled to said second current handling terminal of said second NMOS transistor, a second current handling terminal coupled to said first supply voltage, and a gate terminal driven by an inverse of said first clock signal; and

a capacitor divider circuit coupled between said output terminal and said first supply voltage, a common node of said capacitor divider circuit being coupled to said second current handling terminal of said second NMOS transistor;

wherein said third NMOS transistor is turned off when said switch circuit is turned off; and

said capacitor divider circuit generates a compensating charge at said output terminal, said compensating charge being derived from a channel charge originated from said gate terminal of said first NMOS transistor when said switch circuit is turned off.

43. The switch circuit of claim 42, wherein said capacitor divider circuit comprises a first capacitor and a second capacitor having equal capacitance.

44. The switch circuit of claim 17, further comprising:

a fourth NMOS transistor having a first current handling terminal coupled to said second current handling terminal of said third NMOS transistor, a second current handling terminal coupled to said first supply voltage, and a gate terminal driven by an inverse of said first clock signal; and

a capacitor divider circuit coupled between said output terminal and said first supply voltage, a common node of said capacitor divider circuit being coupled to said second current handling terminal of said third NMOS transistor;

wherein said fourth NMOS transistor is turned off when said switch circuit is turned off; and

said capacitor divider circuit generates a compensating charge at said output terminal, said compensating charge being derived from a channel charge originated from said gate terminal of said first NMOS transistor when said switch circuit is turned off.

45. The switch circuit of claim 42, wherein said capacitor divider circuit comprises a first capacitor and a second capacitor having equal capacitance.

38. A method for selectively coupling an input voltage terminal to an output voltage terminal, comprising:

coupling a switching device between said input voltage terminal and said output voltage terminal;

precharging a charge storage device to a precharge voltage;

coupling said charge storage device between said input terminal and a control terminal of said switching device, causing said switching device to become conductive;

disconnecting said charge storage device from said input terminal and said control terminal of said switching device;

connecting said control terminal of said switching device to a first supply voltage, causing said switching device to become nonconductive;

coupling a capacitor divider circuit between said output terminal and said first supply voltage;

directing a channel charge from said control terminal of said switching device to a common node of said capacitor divider circuit; and

generating a compensating charge at said output terminal, said compensating charge being derived from said channel charge and proportional to a ratio of capacitance values of said capacitor divider circuit;

wherein said compensating charge generated at said output terminal cancels an injected charge at said output terminal.

46. A method for canceling charge injection at an output terminal of a switch circuit said switch circuit comprising a switching device, said method comprising:

coupling a capacitor divider circuit between said output terminal of said switch circuit and a first supply voltage;

directing a channel charge from a control terminal of said switching device to a common node of said capacitor divider circuit; and

generating a compensating charge at said output terminal of said switch circuit, said compensating charge being derived from said channel charge and proportional to a ratio of capacitance values of said capacitor divider circuit;

wherein said compensating charge generated at said output terminal cancels an injected charge at said output terminal.

47. The method of claim 46, wherein said capacitor divider circuit comprises a first capacitor and a second capacitor having equal capacitance.

49. The method of claim 46, wherein said switching device comprises one of an NMOS transistor, a PMOS transistor, and a transmission gate comprising a parallel connection of an NMOS transistor and a PMOS transistor.

50. The method of claim 46, wherein said first supply voltage comprises a ground voltage.

48. A switch circuit for selectively coupling an input terminal to an output terminal comprising:

a switching device coupled between said input terminal and said output terminal, said switching device having a control terminal coupled to a control circuit for turning said switching device on or off;

a first switch coupled to said control terminal, said first switch having a first position being an open circuit and a second position coupled to a first supply voltage; and

a capacitor divider circuit coupled between said output terminal and said first supply voltage, a common node of said capacitor divider circuit being coupled to said first switch;

wherein said first switch operates in response to a first clock signal and is in said first position when said switching device is turned off; and

said capacitor divider circuit generates a compensating charge at said output terminal, said compensating charge being derived from a channel charge originated from said control terminal of said switching device when said switching device is turned off.

51. The method of claim 48, wherein generating a compensating charge at said output terminal of said switch circuit comprises:

dividing said channel charge into half to generate said compensating charge.

52. The switch circuit of claim 48, wherein said switching device comprises one of an NMOS transistor, a PMOS transistor, and a transmission gate comprising a parallel connection of an NMOS transistor and a PMOS transistor.

53. The switch circuit of claim 48, wherein said first supply voltage comprises a ground voltage.

54. The switch circuit of claim 48, wherein said capacitor divider circuit comprises a first capacitor and a second capacitor having equal capacitance and said capacitor divider circuit divides said channel charge into half to generate said compensating charge.