Fail-safe zero delay buffer with automatic internal reference

• US 6,956,419 B1
• Filed: 04/28/2004
• Issued: 10/18/2005
• Est. Priority Date: 08/13/2001
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Mann, Eric N., Wunner, John J.
• Primary Examiner(s): Lam, Tuan T.
• Assistant Examiner(s): COX, CASSANDRA F
• Application Number:
  US10/833,357
• Time in Patent Office: 538 Days
• Field of Search: 327/162, 327/161, 327/141, 327/147, 327/156, 327/261
• US Class Current: 327/162
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/089 the phase or frequency detector generating up-down pulses H03L7/087 takes precedence
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/23 with pulse counters or frequency dividers

Abstract

An apparatus comprising a first circuit and a second circuit. The first circuit may comprise a control circuit and an oscillator. The control circuit may be configured to generate a control signal in response to a first reference signal and a second reference signal. The oscillator may be configured to generate the second reference signal in response to the control signal and a timing signal. The control signal is generally held when the first reference signal is lost. The second circuit may be configured to generate one or more output signals in response to the second reference signal and one of the one or more output signals. The one or more output signals may have a controlled delay with respect to the first reference signal.

Claims

1. An apparatus comprising:

a first circuit comprising (i) a control circuit configured to generate a control signal in response to a first reference signal and a second reference signal and (ii) an oscillator configured to generate said second reference signal in response to said control signal and a timing signal, wherein said control signal is held when said first reference signal is lost; and

a second circuit configured to generate one or more output signals in response to said second reference signal and one of said one or more output signals, wherein said one or more output signals have a controlled delay with respect to said first reference signal and said timing signal is generated independently of said one or more output signals.

2. The apparatus according to claim 1, wherein:

a frequency and a phase of said second reference signal are (i) adjusted in response to said first reference signal and (ii) held when said first reference signal is lost.

3. The apparatus according to claim 1, wherein:

said first reference signal comprises an external timing signal.

4. The apparatus according to claim 1, wherein said first circuit comprises a digitally controlled reference loop circuit.

5. The apparatus according to claim 1, wherein said controlled delay is substantially zero with respect to said first reference signal.

6. The apparatus according to claim 1, wherein said second circuit comprises:

a phase locked loop (PLL) circuit configured to generate a clock signal in response to said second reference signal and said one of said one or more output signals.

7. The apparatus according to claim 6, wherein said PLL circuit comprises an analog PLL circuit.

8. The apparatus according to claim 6, wherein said second circuit further comprises:

a buffer circuit configured to generate said one or more output signals in response to said clock signal.

9. The apparatus according to claim 1, wherein said second circuit comprises a divide-by-N circuit configured to divide said one of said one or more output signals.

10. The apparatus according to claim 1, wherein said oscillator comprises a voltage controlled crystal oscillator (VCXO).

11. The apparatus according to claim 1, wherein said oscillator is an oscillator selected from the group consisting of voltage controlled oscillators (VCOs), current controlled oscillators (ICOs), digitally controlled oscillators, digitally controlled crystal oscillators, LC oscillators, RC oscillators, and ring oscillators.

12. The apparatus according to claim 1, wherein said control circuit comprises a phase detector circuit configured to adjust a phase of said second reference signal in response to (i) said first reference signal and (ii) said second reference signal.

13. The apparatus according to claim 1, wherein said first circuit further comprises a divide-by-N circuit configured to divide a frequency of said first reference signal.

14. The apparatus according to claim 1, wherein said apparatus is implemented on a single integrated circuit chip.

15. An apparatus for generating one or more output signals comprising:

means for generating a second reference signal in response to (i) a first reference signal and (ii) a crystal oscillator signal, wherein (a) a frequency and a phase of said second reference signal are (i) adjusted in response to said first reference signal and (ii) held when said first reference signal is lost and (b) said crystal oscillator signal is generated independently of said one or more output signals; and

means for generating said one or more output signals in response to said second reference signal and one of said one or more output signals.

16. A method of generating one or more output signals comprising the steps of:

(A) generating a second reference signal in response to (i) a first reference signal and (ii) a crystal oscillator signal, wherein a frequency and a phase of said second reference signal are (i) adjusted in response to said first reference signal and (ii) held when said first reference signal is lost and said crystal oscillator signal is generated independently of said one or more output signals; and

(B) generating said one or more output signals in response to said second reference signal and one of said one or more output signals.

17. The method according to claim 16, wherein said second reference signal is phase locked to said first reference signal.

18. The method according to claim 16, wherein step A further comprises the step of dividing said first reference signal by an integer value N.

19. The method according to claim 16, wherein a delay of each of said one or more output signals with respect to said second reference signal is one of (i) a controlled delay, (ii) a substantially zero delay and (iii) a controlled substantially zero delay.

20. An apparatus comprising:

a digitally controlled reference loop circuit configured to generate a reference signal in response to (i) an external timing signal and (ii) a crystal oscillator signal, wherein a frequency and a phase of said reference signal are (i) adjusted in response to said external timing signal and (ii) held when said external timing signal is lost; and

a second circuit (i) configured to generate one or more output signals in response to said reference signal and one of said one or more output signals and (ii) comprising a divide-by-N circuit configured to divide said one of said one or more output signals, wherein said crystal oscillator signal is generated independently of said one or more output signals.