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Generation and measurement of timing delays by digital phase error compensation

  • US 6,956,422 B2
  • Filed: 12/23/2003
  • Issued: 10/18/2005
  • Est. Priority Date: 03/17/2003
  • Status: Expired due to Fees
First Claim
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1. An apparatus comprisinga clock for producing regular clock pulses;

  • a voltage converter for producing a voltage that is directly proportional to the difference between a triggering pulse and a clock pulse;

    an analog-to-digital converter for converting a voltage produced by the voltage converter to a digital value; and

    a summing circuit coupled to the analog-to-digital converter for producing a signal related to the sum of (i) a first time related to a predetermined number of clock pulses and (ii) a second time related to the digital value.

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