Generation and measurement of timing delays by digital phase error compensation
First Claim
1. An apparatus comprisinga clock for producing regular clock pulses;
- a voltage converter for producing a voltage that is directly proportional to the difference between a triggering pulse and a clock pulse;
an analog-to-digital converter for converting a voltage produced by the voltage converter to a digital value; and
a summing circuit coupled to the analog-to-digital converter for producing a signal related to the sum of (i) a first time related to a predetermined number of clock pulses and (ii) a second time related to the digital value.
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Accused Products
Abstract
A circuit and method for generating a delayed event following a trigger pulse occurring at a random time between clock pulses is disclosed. The circuit includes a clock circuit, a voltage converter, an analog-to-digital converter circuit, a memory storage circuit, and a summing circuit. The method includes representing the time between the triggering pulse and a subsequent clock pulse as a voltage, converting the voltage to a stored digital value, and defining a desired delay time by adding a first time determined by counting a predetermined number of clock cycles to a second time determined by converting the stored digital value first to an analog value and then to a time value.
35 Citations
51 Claims
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1. An apparatus comprising
a clock for producing regular clock pulses; -
a voltage converter for producing a voltage that is directly proportional to the difference between a triggering pulse and a clock pulse;
an analog-to-digital converter for converting a voltage produced by the voltage converter to a digital value; and
a summing circuit coupled to the analog-to-digital converter for producing a signal related to the sum of (i) a first time related to a predetermined number of clock pulses and (ii) a second time related to the digital value. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A method for generating delayed events, the method comprising
representing the time between a triggering pulse and a subsequent clock pulse as a voltage; -
converting the voltage to a stored digital value; and
defining a desired delay time following the triggering pulse by (i) identifying a first time and (ii) adding to the first time a second time determined by converting the stored digital value to an analog value and converting the analog value to a time value. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33)
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34. Apparatus for generating a delayed event, the apparatus comprising
first means for producing regular clock pulses; -
second means for producing a voltage that is proportional to the difference between a triggering pulse and a clock pulse;
third means for converting a voltage produced by the second means to a digital value; and
fourth means for producing a signal related to the sum of (i) a first time related to a predetermined number of clock pulses and (ii) a second time related to the digital value, the fourth means coupled to the third means. - View Dependent Claims (35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51)
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Specification