Method and device for timing random reading of a memory device

• US 6,956,787 B2
• Filed: 11/03/2003
• Issued: 10/18/2005
• Est. Priority Date: 11/06/2002
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Scotti, Massimiliano, Confalonieri, Emanuele, Ferrario, Marco, Lisi, Carlo
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US10/700,322
• Publication Number:
  US 20040151035A1
• Time in Patent Office: 715 Days
• Field of Search: 365/233, 365/191, 365/195, 365/196, 365/189.11
• US Class Current: 365/185.17
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A device for timing random reading of a memory device with a data access time, in which reading is performed by a succession of consecutive operations, the timing device being designed to generate, for each operation, a corresponding timing signal such as to cause, whatever the operating condition of the memory device, the corresponding operation to last for a time equal to a respective fixed duration, which is determined so as to guarantee completion of the operation in the worst operating condition of the memory device within the fixed duration; the sum of the fixed durations being equal to the data access time of the memory device.

Claims

1. A method for timing random reading of a memory device with a data access time, said reading being made up of a succession of consecutive operations, wherein each of said operations has, whatever the operating condition of said memory device, a fixed predetermined duration such as to guarantee completion of the operation within said fixed predetermined the worst operating condition of said memory device, the sum of the fixed predetermined durations of said operations being equal to said data access time of said memory device.

2. The timing method according to claim 1, wherein each of said operations making up said reading is started immediately at an end of the preceding operation.

3. The timing method according to claim 1, wherein said fixed predetermined duration is assigned to the corresponding operation in a design stage of said memory device.

4. The timing method according to claim 1, wherein each of said operations has a fixed predetermined duration, which is irrespective of the temperature variations of said memory device.

5. The timing method according to claim 1, wherein each of said operations has a fixed predetermined time duration, which is irrespective of the variations in a supply voltage of said memory device.

6. A device for timing random reading of a memory device with a data access time, said reading being made up of a succession of consecutive operations, said timing device comprising signal generating means, designed to generate, for each said operation, a corresponding timing signal such as to cause, whatever the operating condition of said memory device, the corresponding operation to last for a fixed predetermined duration such as to guarantee completion of said operation in the worst operating condition of said memory device, the sum of the durations of said operations being equal to said data access time of said memory device.

7. The timing device according to claim 6, wherein said signal generating means comprise a plurality of timing blocks, each of which generates a timing signal designed to drive termination of the respective operation, and is supplied at input to a timing block associated to a subsequent operation, for driving start of the latter.

8. The timing device according to claim 7, wherein each timing block comprises at least one input receiving a current which is constant and is irrespective of variations in temperature and supply voltage of said memory device, and at least one output supplying said timing signal.

9. The timing device according to claim 8, wherein said signal generating means further comprise at least one voltage generating block having an output connected to said input of said timing blocks for supplying the timing blocks with said constant current.

10. The timing device according to claim 9, wherein said voltage generating block comprises at least one NMOS cascode transistor and a resistor manufactured using an n-well technology.

11. The timing device according to claim 10, wherein said voltage generating block comprises a supply line set at the supply voltage;

a ground line set at the ground voltage;

at least one PMOS transistor connected to said output and to said supply line, said resistor being connected to said ground line, and said NMOS transistor being arranged between said PMOS transistor and said resistor.

12. The timing device according to claim 10, wherein said NMOS transistor has a gate terminal set at a constant gate voltage, a source terminal connected to said resistor, and a drain terminal connected to the drain terminal of said PMOS transistor.

13. The timing device according to claim 6, wherein each timing block comprises a supply line set at the supply voltage;

a ground line set at the ground voltage;

a signal generator stage, which is designed to generate said timing signal having a fixed duration correlated to the fixed predetermined time of a respective operation; and

a time duration regulation stage, which is designed to regulate said duration of said timing signal and is connected in series to said signal generator stage between said supply line and said ground line.

14. The timing device according to claim 13, wherein said signal generator stage and said duration regulating branch are connected to said constant current input so as to define with the voltage generating block a current mirror.

15. The timing device according to claim 14, wherein said signal generator stage comprises at least one NMOS cascode transistor.

16. The timing device according to claim 13, wherein said duration regulating branch comprises a plurality of capacitors connected in parallel to one another, and a plurality of selector means, designed to connect selectively each said capacitor to said duration regulating branch.

17. The timing device according to claim 16, wherein said signal generator stage comprises at least one PMOS transistor connected to said supply line, at least one NMOS transistor connected to said NMOS transistor at an intermediate node, and at least one logic gate arranged between said intermediate node and said output.