Noninterfering multiply-MAC (multiply accumulate) circuit

• US 6,957,242 B1
• Filed: 08/06/2001
• Issued: 10/18/2005
• Est. Priority Date: 10/26/2000
• Status: Expired due to Term

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Snyder, Warren
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US09/923,461
• Time in Patent Office: 1,534 Days
• Field of Search: 708/490, 708/523
• US Class Current: 708/490
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence

Abstract

A noninterfering multiply-MAC (multiply accumulate) circuit is described. The circuit is operational to perform a MAC (multiply accumulate) operation and to perform a multiply operation without interfering with the accumulate value of the MAC operation. The circuit includes a first register, a second register, a multiplier circuit, and an accumulate circuit. The first register is addressable using either a primary first address or an alias first address. Moreover, the second register is addressable using either a primary second address or an alias second address. The multiplier circuit performs a multiply operation to generate a product value based on the data in the first and second registers after a write operation to either the first register or the second register. The accumulate circuit performs an accumulate operation to generate an accumulate value if either the alias first address or the alias second address is used in the write operation.

Claims

1. A circuit for selecting a multiply operation or a MAC (multiply accumulate) operation comprising:

a first register operative to store a first data, wherein said first register is addressable using a first address which enables said multiply operation and disables an accumulate operation and is addressable using a second address which enables a MAC operation; and

a second register operative to store a second data, wherein said second register is addressable using a third address which enables said multiply operation and disables said accumulate operation and is addressable using a fourth address which enables said MAC operation.

2. A circuit as recited in claim 1 further comprising:

a multiplier circuit coupled to said first and second registers, wherein said multiplier circuit is operative to perform said multiply operation to generate a product value based on data in said first and second registers after a write operation is performed on any one of said first and second registers; and

an accumulator circuit coupled to said multiplier circuit, wherein said accumulator circuit is operative to perform said accumulate operation to generate an accumulate value based on said product value and a previous accumulate value if any one of said second and fourth addresses is used in said write operation.

3. A circuit as recited in claim 2 wherein if any one of said first and third addresses is used in said write operation, said previous accumulate value is not changed.

4. A circuit as recited in claim 1 wherein said first address is a primary address and wherein said second address is an alias address.

5. A circuit as recited in claim 1 wherein said third address is a primary address and wherein said fourth address is an alias address.

6. A circuit for selectively performing a multiply operation and a MAC (multiply accumulate) operation, comprising:

a first register operative to store a first data, wherein said first register is addressable using a first address which indicates said multiply operation is selected and is addressable using a second address which indicates said MAC operation is selected;

a second register operative to store a second data, wherein said second register is addressable using a third address which indicates said multiply operation is selected and is addressable using a fourth address which indicates said MAC operation is selected;

a multiplier circuit coupled to said first and second registers, wherein said multiplier circuit is operative to perform said multiply operation to generate a product value based on data in said first and second registers after a write operation is performed on any one of said first and second registers; and

an accumulator circuit coupled to said multiplier circuit, wherein said accumulator circuit is operative to perform an accumulate operation to generate an accumulate value based on said product value and a previous accumulate value if any one of said second and fourth addresses is used in said write operation.

7. A circuit as recited in claim 6 wherein said first address is a primary address and wherein said second address is an alias address.

8. A circuit as recited in claim 6 wherein said third address is a primary address and wherein said fourth address is an alias address.

9. A circuit as recited in claim 6 wherein if any one of said first and third addresses is used in said write operation, said previous accumulate value is not changed.

10. A circuit as recited in claim 6 wherein after a first MAC operation is performed and before a second MAC operation is performed, a first multiply operation is performed without changing a first accumulate value associated with said first MAC operation.

11. A controller comprising:

a first register operative to store a first data, wherein said first register is addressable using a first address which indicates a multiply operation is selected and is addressable using a second address which indicates a MAC (multiply accumulate) operation is selected;

a second register operative to store a second data, wherein said second register is addressable using a third address which indicates said multiply operation is selected and is addressable using a fourth address which indicates said MAC operation is selected;

a multiplier circuit coupled to said first and second registers, wherein said multiplier circuit is operative to perform said multiply operation to generate a product value based on data in said first and second registers after a write operation is performed on any one of said first and second registers; and

an accumulator circuit coupled to said multiplier circuit, wherein said accumulator circuit is operative to perform an accumulate operation to generate an accumulate value based on said product value and a previous accumulate value if any one of said second and fourth addresses is used in said write operation.

12. A controller as recited in claim 11 wherein said first address is a primary address and wherein said second address is an alias address.

13. A controller as recited in claim 11 wherein said third address is a primary address and wherein said fourth address is an alias address.

14. A controller as recited in claim 11 wherein if any one of said first and third addresses is used in said write operation, said previous accumulate value is not changed.

15. A controller as recited in claim 11 wherein after a first MAC operation is performed and before a second MAC operation is performed, a first multiply operation is performed without changing a first accumulate value associated with said first MAC operation.

16. A controller comprising:

a first register operative to store a first data, wherein said first register is addressable using a first address which disables an accumulate operation and is addressable using a second address which enables said accumulate operation; and

a second register operative to store a second data, wherein said second register is addressable using a third address which disables said accumulate operation and is addressable using a fourth address which enables said accumulate operation.

17. A controller as recited in claim 16 further comprising:

a multiplier circuit coupled to said first and second registers, wherein said multiplier circuit is operative to perform a multiply operation to generate a product value based on data in said first and second registers after a write operation is performed on any one of said first and second registers; and

an accumulator circuit coupled to said multiplier circuit, wherein said accumulator circuit is operative to perform said accumulate operation to generate an accumulate value based on said product value and a previous accumulate value if any one of said second and fourth addresses is used in said write operation.

18. A controller as recited in claim 17 wherein if any one of said first and third addresses is used in said write operation, said previous accumulate value is not changed.

19. A controller as recited in claim 16 wherein said first address is a primary address and wherein said second address is an alias address.

20. A controller as recited in claim 16 wherein said third address is a primary address and wherein said fourth address is an alias address.

21. A method of selectively performing a multiply operation and a MAC (multiply accumulate) operation, comprising the steps of:

a) writing a first data to a first register using one of a first address which indicates said multiply operation is selected and a second address which indicates said MAC operation is selected;

b) performing said multiply operation using said first data and a second data stored in a second register to generate a product value; and

c) performing an accumulate operation to generate an accumulate value based on said product value and a previous accumulate value if said second address is used in said step a).

22. A method as recited in claim 21 wherein said first address is a primary address and wherein said second address is an alias address.

23. A method as recited in claim 21 wherein if said first address is used in said step a), said previous accumulate value is not changed.