System and method for detecting program hazards in processors with unprotected pipelines

• US 6,957,325 B1
• Filed: 07/01/2002
• Issued: 10/18/2005
• Est. Priority Date: 07/01/2002
• Status: Active Grant

• Current Assignee: MACOM Technology Solutions Holdings, Inc.
• Original Assignee: Mindspeed Technologies Inc. (MACOM Technology Solutions Holdings, Inc.)
• Inventors: Xu, Chao, Mathur, Rajat, Chang, En-Shou, Siska, Charles P.
• Primary Examiner(s): Vital, Pierre M.
• Assistant Examiner(s): ROJAS, MIDYS
• Application Number:
  US10/188,247
• Time in Patent Office: 1,205 Days
• Field of Search: 711/140, 712/226, 712/229, 717/127
• US Class Current: 712/226
• CPC Class Codes: G06F 11/3604 Software analysis for verifying properties of programs byte-code verification G06F9/44589

Abstract

A process and system for analyzing executable portion of computer code for processors with unprotected pipelines is provided. The process assumes a worst set of current processor states; analyzes plural control paths for possible hazards by computing an induced set of processor states after executing a computer instruction; and adjusts the worst set of current processor states based on program annotations to the computer instruction.

Claims

1. A method for analyzing executable portion of computer code for processors with unprotected pipelines, comprising:

assuming a worst set of current processor states for a processor with unprotected pipelines;

analyzing plural control paths for possible hazards by computing an induced set of processor states after executing a computer instruction; and

adjusting the worst set of current processor states based on program annotations to the computer instruction.

2. The method of claim 1, further comprising:

determining if the adjusted set of current machine states is different from a previously determined set of processor states; and

updating the computed induced set of processor states associated with the instruction, if the adjusted set of current processor states is different from the previously determined set of processor states.

3. The method of claim 2, further comprising:

using the computed set of processor states for determining hazards in another computer instruction.

4. A computer-readable medium storing computer-executable process steps of a process for use in a computer system for analyzing executable portion of computer code for processors with unprotected pipelines, comprising:

assuming a worst set of current processor states;

analyzing plural control paths for possible hazards by computing an induced set of processor states after executing a computer instruction; and

adjusting the worst set of current processor states based on program annotations to the computer instruction.

5. The computer readable medium of claim 4, further comprising:

determining if the adjusted set of current machine states is different from a previously determined set of processor states; and

updating the computed induced set of processor states associated with the instruction, if the adjusted set of current processor states is different from the previously determined set of processor states.

6. The computer readable medium of claim 4, further comprising:

using the computed set of processor states for determining hazards in the next computer instruction.

7. Computer-executable code for analyzing executable portion of computer code for processors with unprotected pipelines, comprising:

assuming a worst set of current processor states;

analyzing plural control paths for possible hazards by computing an induced set of processor states after executing a computer instruction; and

adjusting the worst set of current processor states based on program annotations to the computer instruction.

8. Computer-executable code of claim 7, further comprising:

determining if the adjusted set of current machine states is different from a previously determined set of processor states; and

updating the computed induced set of processor states associated with the instruction, if the adjusted set of current processor states is different from the previously determined set of processor states.

9. Computer-executable code of claim 7, further comprising:

using the computed set of processor states for determining hazards in another computer instruction.

10. A system for analyzing executable portion of computer code, comprising:

a processor that analyzes plural control paths for possible hazards by computing an induced set of processor states after executing a computer instruction; and

adjusting a set of current processor states based on program annotations to the computer instruction.

11. The system of claim 10, wherein the processor

determines if the adjusted set of current processor states is different from a previously determined set of processor states;

and

updates the computed induced set of processor states associated with the instruction, if the adjusted set of current processor states is different from the previously determined set of processor states.

12. The system of claim 10, wherein the processor uses the computed set of processor states for determining hazards in another computer instruction.