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Method and apparatus for routing nets in an integrated circuit layout

  • US 6,957,408 B1
  • Filed: 08/09/2002
  • Issued: 10/18/2005
  • Est. Priority Date: 01/22/2002
  • Status: Expired due to Fees
First Claim
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1. A method of providing routes for a plurality of elements within a region of an integrated circuit (“

  • IC”

    ) layout, the method comprising;

    a) selecting a set of elements to be routed in the IC layout region;

    b) identifying a topological route for the set of elements, wherein a topological route is a route that connects the elements of the set and represents a set of diffeomorphic geometric routes; and

    c) generating a geometric route for the set of elements, wherein a geometric route comprises a plurality of coordinates on the IC layout.

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