Gridless IC layout and method and apparatus for generating such a layout

• US 6,957,411 B1
• Filed: 08/26/2002
• Issued: 10/18/2005
• Est. Priority Date: 06/03/2001
• Status: Expired due to Fees

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Teig, Steven, Caldwell, Andrew, Jacques, Etienne
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Kik, Phallaka
• Application Number:
  US10/229,108
• Time in Patent Office: 1,149 Days
• Field of Search: 716/13, 716/14, 716/9, 716/10, 716/21, 700/121, 430/5, 378/35, 378/5
• US Class Current: 716/55
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

Some embodiments of the invention provide a method of routing nets in a region of an integrated-circuit (“IC”) layout. The method selects a net that has several routable elements. It then defines a route for the net. To define the route, the method uses a wiring model that specifies preferred non-Manhattan wiring directions. It also uses a manufacturing grid as the only grid for constraining the location of interconnect lines for connecting the net'"'"'s routable elements.

Claims

1. A region of an integrated-circuit (“

IC”

) layout comprising;

a) a plurality of nets having a plurality of routable elements;

b) a plurality of routes for connecting the routable elements of nets, wherein the routes traverse preferred non-Manhattan interconnect directions that are specified by a wiring model;

c) wherein the only grid that the routes are aligned with is the manufacturing grid.

2. The IC-layout region of claim 1, wherein the non-Manhattan wiring directions are at angles of ±

A°

with respect to a coordinate axis of the layout, wherein A does not equal 0 or 90.

3. The IC-layout region of claim 2, wherein A equals 45.

4. The IC-layout region of claim 1, wherein the wiring model specifies horizontal, vertical, and ±

45°

directions.

5. The IC-layout region of claim 1, wherein the routes comply with design rules.

6. The IC-layout region of claim 5, wherein the design rules specify minimum spacing between routes.

7. The IC-layout region of claim 5, wherein the design rules specify minimum spacing between routes and layout items unrelated to the routes.

8. The IC-layout region of claim 1, wherein the region is the entire layout.

9. The IC-layout region of claim 1, wherein the region is a portion of the layout.

10. A method of routing nets in a region of an integrated-circuit (“

IC”

) layout, the method comprising;

a) selecting a net having a plurality of routable elements;

b) defining a route for the net by using a wiring model that specifies preferred non-Manhattan wiring directions, and using a manufacturing grid as the only grid for constraining location of interconnect lines for connecting the net'"'"'s routable elements.

11. The method of claim 10, wherein the wiring model specifies horizontal, vertical and ±

45 degree diagonal lines.

12. The method of claim 10 further comprising using design rules to constrain the location of interconnect lines for connecting the net'"'"'s routable elements.

13. The method of claim 12, wherein the design rules specify minimum spacing between routes.

14. The method of claim 12, wherein the design rules specify minimum spacing between routes and layout items unrelated to the routes.

15. The method of claim 10, wherein using the manufacturing grid comprises using the manufacturing grid as the only grid for defining a set of vertices that define the route.

16. The method of claim 15, wherein defining the set of vertices includes using design rules to define the boundary of a routing area that contains the set of vertices.

17. A computer readable medium comprising a computer program having executable code, the computer program for routing nets in a region of an integrated-circuit layout, the computer program comprising sets of instructions for:

a) selecting a net having a plurality of routable elements;

b) defining a route for the net by using a wiring model that specifies non-Manhattan wiring directions, and using a manufacturing grid as the only grid for constraining location of interconnect lines for connecting the net'"'"'s routable elements.

18. The computer readable medium of claim 17, wherein the wiring model specifies horizontal, vertical and ±

45 degree diagonal lines.

19. The computer readable medium of claim 17, wherein the computer program further comprises a set of instructions for using design rules to constrain the location of interconnect lines for connecting the net'"'"'s routable elements.

20. The computer readable medium of claim 17, wherein the set of instructions for using the manufacturing grid comprises a set of instructions for using the manufacturing grid as the only grid for defining a set of vertices that define the route.

21. The computer readable medium of claim 20, wherein the set of instructions for defining the set of vertices includes a set of instructions for using design rules to define the boundary of a routing area that contains the set of vertices.

22. A method of manufacturing an integrated circuit, the integrated circuit having a plurality of wiring layers, the method comprising:

a) specifying a layout for the integrated circuit by using a wiring model that specifies preferred non-Manhattan wiring directions, and using a manufacturing grid as the only grid for constraining location of interconnect lines for routable elements in the layout;

b) using the layout to fabricate the integrated circuit.

23. The method of claim 22, wherein using the layout to fabricate the integrated circuit comprises using the layout to generate a mask for the particular wiring layer.

24. The method of claim 23, wherein the mask has patterns that are in shape of interconnect lines.

25. The method of claim 22, wherein the wiring model further specifies Manhattan wiring directions.

26. The method of claim 25, wherein the wiring model specifies Manhattan and non-Manhattan wiring directions on the same wiring layer.

27. A integrated circuit mask having etching patterns that are based on wiring a model that specifies preferred non-Manhattan wiring directions and that uses a manufacturing grid as the only grid for constraining location of the wiring.

28. The mask of claim 27, wherein the wiring model further specifies Manhattan wiring directions.

29. The mask of claim 28, wherein the wiring model specifies Manhattan and non-Manhattan wiring directions on a same wiring layer.

30. A integrated-circuit mask having etching patterns in non-Manhattan directions, wherein the etching patterns of the mask align with a manufacturing grid, wherein the manufacturing grid is the only grid with which the mask'"'"'s etching pattern aligns.

31. The mask of claim 30 further having etching patterns in Manhattan direction.