Semiconductor memory pipeline buffer

• US 6,958,507 B2
• Filed: 02/10/2004
• Issued: 10/25/2005
• Est. Priority Date: 08/04/2003
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Sakata, Takeshi, Watanabe, Takao, Atwood, Bryan
• Primary Examiner(s): Abraham, Fetsum
• Application Number:
  US10/774,586
• Publication Number:
  US 20050029551A1
• Time in Patent Office: 623 Days
• Field of Search: 257296-310, 257/315, 257/316
• US Class Current: 257/296
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 2207/2281 Timing of a read operation
• CPC Class Codes: G11C 2207/229 Timing of a write operation
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1042 using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: H10B 12/482 Bit lines
• CPC Class Codes: H10B 12/485 Bit line contacts

Abstract

A high capacity, fast access dynamic random access memory is provided. Furthermore, a pipelined write method can be realized at each array block by affixing a latch between the sense amplifier and write data line for each column. In this manner, a data write phase can occur simultaneously with the pre-read phase of the following address. Using this method, the effective access speed to the array block can be increased, yielding a fast access cache memory.

Claims

1. A memory, comprising:

a memory column including,

a plurality of word line pairs,

a pair of data lines, wherein the plurality of word line pairs intersects the pair of data lines at intersections, and

memory cells, wherein each memory cell is coupled to one of the plurality of word line pairs and the pair of data lines, wherein each of the plurality of word line pairs include a read word line and a write word line, and the read word line and the write word line which are included in different word line pairs can both be active simultaneously,

wherein the pair of data lines includes a read data line and a write data line,

wherein the memory further comprises;

a latch having a latch input and a latch output, wherein the latch input is connected to the read data line and to an input data line, wherein the latch is configured to hold data of the input data line or data of a connected memory cell, wherein the latch output is connected to the write data line, and

wherein the memory column further comprises a sense amplifier configured to connect the read data line to the latch, wherein the read data line is connected to a sense amplifier input, wherein a sense amplifier output is connected to the latch input.

2. The memory of claim 1, further comprising a latch connected to the write word line, wherein the latch is configured to hold a decoded write word line activation signal based on a previously decoded address to drive the paired read word line.

3. The memory of claim 1, wherein when a same memory cell receives a consecutive read access, the memory is configured to read data held in a connected latch of the same memory cell and not data stored in the same memory cell.

4. The memory of claim 1, wherein at least one of the memory cells is one of:

a three-transistor dynamic memory cell;

or

a three-transistor dynamic memory cell including a write transistor, wherein the write transistor is a thin-channel polysilicon transistor having a channel region thickness of 5 nanometers or less.

5. The memory of claim 1, wherein when a same memory cell receives a consecutive write access from an external input data bus, the latch stores data from the external input data without reading data from the memory cell.

6. The memory of claim 1, further comprising another memory column configured like the memory column, wherein the memory column and the other memory column share the latch, wherein the memory is configured to conserve space on a silicon die in which the memory is fabricated due to sharing of the latch.

7. The memory of claim 1, wherein the latch stores data read out from one of the memory cell in a first cycle and outputs the data to the write data line in a second cycle and wherein another memory cell receives a read access in the second cycle.