Multiple chip semiconductor package

• US 6,958,537 B2
• Filed: 08/04/2004
• Issued: 10/25/2005
• Est. Priority Date: 08/27/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Neo, Yong Loo, Boon, Suan Jeung, Low, Siu Waf, Chua, Swee Kwang, Chia, Yong Poo, Eng, Meow Koon, Huang, Suangwu
• Primary Examiner(s): Zarneke, David A.
• Application Number:
  US10/912,415
• Publication Number:
  US 20050006748A1
• Time in Patent Office: 447 Days
• Field of Search: 257/723, 257/686, 257/724, 257/778
• US Class Current: 257/723
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/06136 Covering only the central area of the surface to be connected, i.e. central arrangements
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/29075 Plural core members
• CPC Class Codes: H01L 2224/2929 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/293 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/8121 using a reflow oven
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 2224/83851 being an anisotropic conductive adhesive
• CPC Class Codes: H01L 2224/90 Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 24/90 Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A semiconductor device package is disclosed. The semiconductor device package may include a variety of semiconductor dice, thereby providing a system on a chip solution. The semiconductor dice are attached to connection locations associated with a conductive trace layer such as through flip-chip technology. A plurality of circuit connection elements is also coupled to the conductive trace layer, either directly or through additional, intervening conductive trace layers. An encapsulation layer may be formed over the dice and substrate. Portions of the circuit connection elements remain exposed through the encapsulation layer for connection to external devices. A plurality of conductive bumps may be formed, each conductive bump being disposed atop an exposed portion of a circuit connection element, to facilitate electrical connection with an external device.

Claims

1. A semiconductor device package comprising:

a substrate;

a first dielectric layer disposed over a surface of the substrate;

a conductive trace layer disposed over the first dielectric layer;

a second dielectric layer disposed over the conductive trace layer, the second dielectric layer defining a plurality of vias therethrough exposing a plurality of connection areas on the conductive trace layer;

a metallization layer electrically coupled with the plurality of connection areas;

a plurality of semiconductor dice, each semiconductor die of the plurality of semiconductor dice having a plurality of signal connection devices, wherein;

the plurality of signal connection devices is electrically coupled with the metallization layer;

an encapsulation layer disposed over the plurality of semiconductor dice; and

a plurality of circuit connection elements electrically coupled to the conductive trace layer, wherein each of the plurality of circuit connection elements extends through the first dielectric layer and the second dielectric layer, and has a portion thereof exposed through the encapsulation layer.

2. The semiconductor device package of claim 1, further comprising a plurality of conductive bumps wherein each conductive bump of the plurality of conductive bumps is electrically coupled with the exposed portion of one of the plurality of circuit connection elements.

3. The semiconductor device package of claim 2, wherein the plurality of conductive bumps is selected from the group consisting of solder bumps, gold stud bumps, copper stud bumps, and plated alloy stud bumps.

4. The semiconductor device package of claim 3, wherein the plurality of signal connection devices comprises solder bumps.

5. The semiconductor device package of claim 1, further comprising a final dielectric layer disposed adjacent the metallization layer and an attachment layer overlaying at least a portion of the final dielectric layer and the metallization layer.

6. The semiconductor device package of claim 5, wherein the attachment layer is selected from the group consisting of anisotropic conducting film, anisotropic conducting paste, nonconductive film, and nonconductive paste.

7. The semiconductor device package of claim 6, wherein the plurality of signal connection devices is selected from the group consisting of gold stud bumps, copper stud bumps, and plated stud bumps.

8. A semiconductor device package comprising:

a substrate;

a first dielectric layer disposed over a surface of the substrate;

a first conductive trace layer disposed over the first dielectric layer;

at least one additional dielectric layer disposed over the first conductive trace layer;

at least one additional conductive trace layer disposed over the at least one additional dielectric layer, the at least one additional dielectric layer being electrically coupled with the first conductive trace layer;

a final dielectric layer disposed over the at least one additional conductive trace layer;

a plurality of semiconductor dice, each semiconductor die of the plurality of semiconductor dice having a plurality of signal connection devices, wherein;

the plurality of signal connection devices is electrically coupled with the at least one additional conductive trace layer;

an encapsulation layer disposed over the plurality of semiconductor dice; and

a plurality of circuit connection elements electrically coupled with the first conductive trace layer, wherein each of the plurality of circuit connection elements extends through the first dielectric layer and the at least one additional dielectric layer, and has a portion thereof exposed through the encapsulation layer.

9. The semiconductor device package of claim 8, further comprising a plurality of conductive bumps wherein each conductive bump of the plurality of conductive bumps is disposed on and electrically coupled with the exposed portion of one of the plurality of circuit connection elements.

10. The semiconductor device package of claim 9, wherein the plurality of conductive bumps is selected from the group consisting of solder bumps, gold stud bumps, copper stud bumps, and plated alloy stud bumps.

11. The semiconductor device package of claim 9, further comprising a plurality of openings in the final dielectric layer exposing a plurality of connection areas on the at least one additional conductive trace layer and wherein the plurality of signal connection devices is electrically coupled with the exposed plurality of connection areas.

12. The semiconductor device package of claim 11, further comprising a metallization layer disposed between the plurality of signal connection devices and the exposed plurality of connection areas.

13. The semiconductor device package of claim 12, further comprising an attachment layer disposed over the final dielectric layer and the metallization layer.

14. The semiconductor device package of claim 13, wherein the attachment layer is selected from the group consisting of anisotropic conducting film, anisotropic conducting paste, nonconductive film, and nonconductive paste.

15. The semiconductor device package of claim 14, wherein the plurality of signal connection devices is selected from the group consisting of gold stud bumps, copper stud bumps, and plated stud bumps.

16. A memory device comprising:

a carrier substrate;

a plurality of electrical contacts coupled with electrical circuitry formed in the carrier substrate; and

at least one semiconductor device package coupled with the electrical circuitry in the carrier substrate, the at least one semiconductor device package comprising;

a substrate;

a first dielectric layer disposed over a surface of the substrate;

a conductive trace layer disposed over the first dielectric layer;

a second dielectric layer disposed over the conductive trace layer, the second dielectric layer defining a plurality of vias therethrough exposing a plurality of connection areas on the conductive trace layer;

a metallization layer electrically coupled with the plurality of connection areas;

a plurality of semiconductor dice, each semiconductor die of the plurality of semiconductor dice having a plurality of signal connection devices wherein the plurality of signal connection devices is electrically coupled with the metallization layer;

an encapsulation layer disposed over the plurality of semiconductor dice; and

a plurality of circuit connection elements electrically coupled to the conductive trace layer, wherein each of the plurality of circuit connection elements extends through the first dielectric layer and the second dielectric layer, and has a portion thereof exposed through the encapsulation layer.

17. A computing system comprising:

a carrier substrate;

a processor operably coupled to circuitry formed in the carrier substrate;

at least one input device operably coupled with the circuitry formed in the carrier substrate;

at least one output device operably coupled with the circuitry formed in the carrier substrate; and

a memory device operably coupled to the circuitry formed in the carrier substrate, the memory device including at least one semiconductor device package, the at least one semiconductor device package comprising;

a substrate;

a first dielectric layer disposed over a surface of the substrate;

a conductive trace layer disposed over the first dielectric layer;

a second dielectric layer disposed over the conductive trace layer, the second dielectric layer defining a plurality of vias therethrough exposing a plurality of connection areas on the conductive trace layer;

a metallization layer electrically coupled with the plurality of connection areas;

a plurality of semiconductor dice, each semiconductor die of the plurality of semiconductor dice having a plurality of signal connection devices wherein the plurality of signal connection devices is electrically coupled with the metallization layer;

an encapsulation layer disposed over the plurality of semiconductor dice; and

a plurality of circuit connection elements electrically coupled to the conductive trace layer, wherein each of the plurality of circuit connection elements extends through the first dielectric layer and the second dielectric layer, and has a portion thereof exposed through the encapsulation layer.

18. A computing system comprising:

a carrier substrate;

at least one input device operably coupled with circuitry formed in the carrier substrate;

at least one output device operably coupled with the circuitry formed in the carrier substrate; and

at least one semiconductor device package operably coupled with the circuitry formed in the carrier substrate, the at least one semiconductor device package comprising;

a substrate;

a first dielectric layer disposed over a surface of the substrate;

a conductive trace layer disposed over the first dielectric layer;

a second dielectric layer disposed over the conductive trace layer, the second dielectric layer defining a plurality of vias therethrough exposing a plurality of connection areas on the conductive trace layer;

a metallization layer electrically coupled with the plurality of connection areas;

a plurality of semiconductor dice, each semiconductor die of the plurality of semiconductor dice having a plurality of signal connection devices wherein the plurality of signal connection devices is electrically coupled with the metallization layer;

an encapsulation layer disposed over the plurality of semiconductor dice; and

a plurality of circuit connection elements electrically coupled to the conductive trace layer, wherein each of the plurality of circuit connection elements extends through the first dielectric layer and the second dielectric layer, and has a portion thereof exposed through the encapsulation layer.