SAR ADC providing digital codes with high accuracy and high throughput performance
First Claim
1. A method of converting a sample of an analog signal to a N-bit digital code, said method being performed in an analog to digital converter (ADC), said method comprising:
- receiving said sample of said analog signal;
resolving P most significant bits (MSBs) of said N-bit digital code from said sample using one of a first reference voltage and a second reference voltage, wherein P is less than N; and
resolving Q bits of said N-bit digital code while using said first reference voltage to generate an equivalent voltage corresponding to said P MSBs and using said second reference voltage to generate an equivalent voltage corresponding to said Q bits,wherein said Q bits form the next MSBs following said P MSBs,further comprising resolving next R bits of said N-bit digital code while using said first reference voltage to generate an equivalent voltage corresponding to both of said P MSBs and said Q bits, and said second reference voltage to generate an equivalent voltage corresponding to said R bits.
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Accused Products
Abstract
An aspect of the invention improves accuracy of digital codes generated at the output of a SAR ADC by using multiple reference voltages. A first reference voltage is used to generate an equivalent voltage corresponding to previous resolved bits and a second reference voltage is used to generate equivalent voltage corresponding to the bits being presently resolved. Another aspect of the present invention provides an ADC with high SNR as well as high throughput performance. Such a feature may be achieved by resolving some of the MSBs of the digital code using a high speed and low SNR DAC and remaining bits of the digital code using a high SNR DAC.
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Citations
52 Claims
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1. A method of converting a sample of an analog signal to a N-bit digital code, said method being performed in an analog to digital converter (ADC), said method comprising:
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receiving said sample of said analog signal; resolving P most significant bits (MSBs) of said N-bit digital code from said sample using one of a first reference voltage and a second reference voltage, wherein P is less than N; and resolving Q bits of said N-bit digital code while using said first reference voltage to generate an equivalent voltage corresponding to said P MSBs and using said second reference voltage to generate an equivalent voltage corresponding to said Q bits, wherein said Q bits form the next MSBs following said P MSBs, further comprising resolving next R bits of said N-bit digital code while using said first reference voltage to generate an equivalent voltage corresponding to both of said P MSBs and said Q bits, and said second reference voltage to generate an equivalent voltage corresponding to said R bits.
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2. A method of converting a sample of an analog signal to a N-bit digital code, said method being performed in an analog to digital converter (ADC), said method comprising:
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receiving said sample of said analog signal; resolving P most significant bits (MSBs) of said N-bit digital code from said sample using one of a first reference voltage and a second reference voltage, wherein P is less than N; and resolving Q bits of said N-bit digital code while using said first reference voltage to generate an equivalent voltage corresponding to said P MSBs and using said second reference voltage to generate an equivalent voltage corresponding to said Q bits, wherein said Q bits form the next MSBs following said P MSBs, further comprises generating said first reference voltage using a first buffer and said second reference voltage using a second buffer. - View Dependent Claims (3, 4, 5, 6, 7)
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8. A method of converting a sample of an analog signal to a N-bit digital code, said method being performed in an analog to digital converter (ADC), said method comprising:
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receiving said sample; resolving at least one most significant bits (MSB) of said N-bit digital code using a first DAC; setting an intermediate digital value to equal said at least one MSB in corresponding bit positions; and resolving at least one of the remaining bits of said MSB using a second DAC starting from said intermediate digital value, wherein each of said at least one MSB and at least one of the remaining bits are resolved according to a successive approximation principle (SAP). - View Dependent Claims (9, 10, 11, 12)
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13. A successive approximation type analog to digital converter (SAR ADC) converting a sample of an input analog signal into an N-bit digital code, said SAR ADC comprising:
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a SAR logic determining said N-bit digital code, said SAR logic providing an intermediate digital value in each iteration according to a comparison result which is based on a comparison of a voltage level equivalent of the intermediate digital value provided in a prior iteration with said sample; a comparator providing said comparison result; and a digital to analog converter (DAC) converting said intermediate value to an equivalent voltage level, said DAC receiving a first reference voltage and a second reference voltage, wherein said DAC generates said voltage level using said first reference voltage for a first subset of bits and said second reference voltage for a second subset of bits, wherein said first subset of bits and said second subset of bits are contained in said intermediate digital value. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. A successive approximation type analog to digital converter (SAR ADC) converting a sample of an input analog signal into an N-bit digital code, said SAR ADC comprising:
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a first digital to analog converter (DAC) converting a first input to an equivalent voltage level; a second digital to analog converter (DAC) converting a second input to an equivalent voltage level wherein said second input comprises N-bits; and a SAR logic sending a first sequence of input bit sets as said first input and determining a corresponding number of most significant bit (MSB) values, wherein each of said first sequence of input bit sets contains a number of bits equaling a number of bits in said first input, said SAR logic setting corresponding MSB positions of an intermediate digital value to the determined MSB values and sending said intermediate digital value as said second input to determine another bit of said N-bit digital code. - View Dependent Claims (24, 25, 26, 27)
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28. A system comprising:
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an analog processor processing an analog signal to generate a sample of an analog signal; a successive approximation digital to analog converter (SAR ADC) converting said sample into an N-bit digital code, said SAR ADC comprising; a SAR logic determining said N-bit digital code, said SAR logic providing an intermediate digital value in each iteration according to a comparison result which is based on a comparison of a voltage level equivalent of the intermediate digital value provided in a prior iteration with said sample; a comparator providing said comparison result; and a digital to analog converter (DAC) converting said intermediate value to an equivalent voltage level, said DAC receiving a first reference voltage and a second reference voltage, wherein said DAC generates said voltage level using said first reference voltage for a first subset of bits and said second reference voltage for a second subset of bits, wherein said first subset of bits and said second subset of bits are contained in said intermediate digital value. - View Dependent Claims (29, 30, 31, 32, 33, 34, 35, 36, 37, 38)
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39. A system comprising:
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an analog processor processing an analog signal to generate a sample of an analog signal; a successive approximation type analog to digital converter (SAR ADC) converting said sample into an N-bit digital code, said SAR ADC comprising; a first comparator providing a comparison result of a first analog signal and said sample; a second comparator providing a comparison result of a second analog signal and said sample; a first digital to analog converter (DAC) receiving said sample and an intermediate P-bit digital value, said first DAC generating said first analog signal based on said intermediate P-bit digital value in each iteration; a second DAC receiving said sample and an intermediate N-bit digital value, said second DAC generating said second analog signal based on said intermediate N-bit digital value in each iteration; and a SAR logic determining said N-bit digital code by resolving a first subset of bits by interfacing with said first DAC and said first comparator, and then resolving a second subset of bits by interfacing with said second DAC and said second comparator, wherein said first subset of bits and said second subset of bits are used to generate said N-bit digital code. - View Dependent Claims (40, 41, 42, 43)
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44. An apparatus converting a sample of an analog signal to a N-bit digital code, said apparatus comprising:
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means for receiving said sample of said analog signal; means for resolving P most significant bits (MSBs) of said N-bit digital code from said sample using one of a first reference voltage and a second reference voltage, wherein P is less than N; and means for resolving Q bits of said N-bit digital code while using said first reference voltage to generate an equivalent voltage corresponding to said P MSBs and using said second reference voltage to generate an equivalent voltage corresponding to said Q bits, wherein said Q bits form the next MSBs following said P MSBs, further comprises means for resolving next R bits of said N-bit digital code while using said first reference voltage to generate an equivalent voltage corresponding to both of said P MSBs and said Q bits, and said second reference voltage to generate an equivalent voltage corresponding to said R bits. - View Dependent Claims (45, 46, 47, 48, 49)
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50. An apparatus converting a sample of an analog signal to a N-bit digital code, said apparatus comprising:
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means for receiving said sample of a voltage level; means for providing said sample of said voltage level as an input to a first digital to analog converter (DAC) to resolve a first subset of bits; and means for providing said sample of said voltage level as an input to a second DAC to resolve a second subset of bits, wherein said first subset of bits and said second subset of bits are used to generate said N-bit digital code, wherein said first subset of bits comprise M most significant bits (MSBs) of said N-bit digital code, wherein said second subset comprises remaining (N−
M bits) of said N-bit digital code, andwherein said first DAC is implemented with a higher speed compared to said second DAC, and said second DAC is implemented with a higher SNR compared to said first DAC such that said ADC is provided with high speed and high SNR. - View Dependent Claims (51, 52)
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Specification