Data writing method for semiconductor memory device and semiconductor memory device

• US 6,958,938 B2
• Filed: 12/09/2004
• Issued: 10/25/2005
• Est. Priority Date: 02/20/2001
• Status: Expired due to Term

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Goda, Akira, Noguchi, Mitsuhiro, Takeuchi, Yuji
• Primary Examiner(s): Phung, Anh
• Assistant Examiner(s): Nguyen, Tuan T.
• Application Number:
  US11/007,461
• Publication Number:
  US 20050157558A1
• Time in Patent Office: 320 Days
• Field of Search: 365/185.22, 365/185.28
• US Class Current: 365/185.22
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3468 Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing

Abstract

A data writing method for a semiconductor memory device includes writing data into the first memory cell, rewriting the data into the first memory cell when an insufficiency of the data of the first memory cell is determined as a result of verifying the data of the first memory cell at one first reference threshold voltage, writing data into the second memory cell following writing the data into the first memory cell, and rewriting the data into the first memory cell following writing the data into the second memory cell when an insufficiency of the data of the first memory cell is determined as a result of verifying the data of the first memory cell at one second reference threshold voltage. The first reference threshold voltage is set to be different from the second reference threshold voltage.

Claims

1. A data writing method for a semiconductor memory device having a first memory cell block capable of rewriting data and having at least one first memory cell;

and a second memory cell block capable of rewriting data and having at least one second memory cell adjoining said first memory cell, said method comprising;

writing data into said first memory cell;

rewriting the data into said first memory cell when an insufficiency of the data of said first memory cell is determined as a result of verifying the data of said first memory cell at one first reference threshold voltage;

writing data into said second memory cell following writing the data into said first memory cell; and

rewriting the data into said first memory cell following writing the data into said second memory cell when an insufficiency of the data of said first memory cell is determined as a result of verifying the data of said first memory cell at one second reference threshold voltage, and said first reference threshold voltage is set to be different from said second reference threshold voltage.

2. The method according to claim 1, wherein said first and second memory cells have a charge accumulation layer, respectively, in which the electric charge is injected or discharged in association with the data to be stored and store the data of 2 values or more as an electric charge amount.

3. The method according to claim 1, wherein said first and second memory cells have a charge accumulation layer, respectively, in which the electric charge is injected or discharged in association with the data to be stored, store the data of 2 values or more as an electric charge amount and store the data of 3 values or more supplied from the outside in association with the data of 2 values of each of said first and second memory cells.

4. The method according to claim 1, wherein each of said first and second memory cells comprises a field effect transistor having at least one charge accumulation layer and at least one control gate.

5. The method according to claim 4, wherein said field effect transistors are formed on the same conductive type well, respectively.

6. The method according to claim 4, wherein said field effect transistors use an FN tunneling current for the writing operation.

7. The method according to claim 4, wherein each of said first and second memory cells includes at least first and second cell transistors adjoined to each other, each of said first and second cell transistors has a source electrode, a drain electrode and said charge accumulation layer, said source electrode of said first cell transistor and said drain electrode of said second cell transistor are connected in series to each other, and a distance between said charge accumulation layer of said first cell transistor and said charge accumulation layer of said second cell transistor is less than twice of a thickness of said charge accumulation layer.

8. The method according to claim 7, wherein the only insulator is formed between the charge accumulation layer of said first memory cell and the charge accumulation layer of said second memory cell.

9. A data writing method for a semiconductor memory device having a memory cell block capable of rewriting data, said memory cell block having at least two first and second memory cells connected in series or in parallel and adjoined to each other, said method comprising:

writing data into said first memory cell;

rewriting the data into said first memory cell when an insufficiency of the data of said first memory cell is determined as a result of verifying the data of said first memory cell at one first reference threshold voltage;

writing data into said second memory cell following writing the data into said first memory cell; and

rewriting the data into said first memory cell following writing the data into said second memory cell when an insufficiency of the data of said first memory cell is determined as a result of verifying the data of said first memory cell at one second reference threshold voltage, and said first reference threshold voltage is set to be different from said second reference threshold voltage.

10. The method according to claim 9, wherein said first and second memory cells have a charge accumulation layer, respectively, in which the electric charge is injected or discharged in association with the data to be stored and store the data of 2 values or more as an electric charge amount.

11. The method according to claim 9, wherein said first and second memory cells have a charge accumulation layer, respectively, in which the electric charge is injected or discharged in association with the data to be stored, store the data of 2 values or more as an electric charge amount and store the data of 3 values or more supplied from the outside in association with the data of 2 values of each of said first and second memory cells.

12. The method according to claim 9, wherein each of said first and second memory cells comprises a field effect transistor having at least one charge accumulation layer and at least one control gate.

13. The method according to claim 12, wherein said field effect transistors are formed on the same conductive type well, respectively.

14. The method according to claim 12, wherein said field effect transistors use an FN tunneling current for the writing operation.

15. The method according to claim 12, wherein each of said first and second memory cells includes at least first and second cell transistors adjoined to each other, each of said first and second cell transistors has a source electrode, a drain electrode and said charge accumulation layer, said source electrode of said first cell transistor and said drain electrode of said second cell transistor are connected in series to each other, and a distance between said charge accumulation layer of said first cell transistor and said charge accumulation layer of said second cell transistor is less than twice of a thickness of said charge accumulation layer.

16. A data writing method for a semiconductor memory device having a memory cell block capable of rewriting data, said memory cell block having at least two first and second memory cells connected in series or in parallel and adjoined to each other, and a data control line of said first memory cell and a data control line of said second memory cell adjoin to each other, said method comprising:

writing data into said first memory cell;

rewriting the data into said first memory cell when an insufficiency of the data of said first memory cell is determined as a result of verifying the data of said first memory cell at one first reference threshold voltage;

writing data into said second memory cell following writing the data into said first memory cell; and

rewriting the data into said first memory cell following writing the data into said second memory cell when an insufficiency of the data of said first memory cell is determined as a result of verifying the data of said first memory cell at one second reference threshold voltage, and said first reference threshold voltage is set to be different from said second reference threshold voltage.

17. The method according to claim 16, wherein said first and second memory cells have a charge accumulation layer, respectively, in which the electric charge is injected or discharged in association with the data to be stored and store the data of 2 values or more as an electric charge amount.

18. The method according to claim 16, wherein said first and second memory cells have a charge accumulation layer, respectively, in which the electric charge is injected or discharged in association with the data to be stored, store the data of 2 values or more as an electric charge amount and store the data of 3 values or more supplied from the outside in association with the data of 2 values of each of said first and second memory cells.

19. The device according to claim 16, wherein each of said first and second memory cells comprises a field effect transistor having at least one charge accumulation layer and at least one control gate,

wherein each of said first and second memory cells includes at least first and second cell transistors adjoined to each other, each of said first and second cell transistors has a source electrode, a drain electrode and said charge accumulation layer, said source electrode of said first cell transistor and said drain electrode of said second cell transistor are connected in series to each other, and a distance between said charge accumulation layer of said first cell transistor and said charge accumulation layer of said second cell transistor is less than twice of a thickness of said charge accumulation layer.

20. The device according to claim 16, wherein each of said first and second memory cells comprises a field effect transistor having at least one charge accumulation layer and at least one control gate,

wherein said field effect transistors are formed on the same conductive type well, respectively.