Enhanced refresh circuit and method for reduction of DRAM refresh cycles

• US 6,958,944 B1
• Filed: 05/26/2004
• Issued: 10/25/2005
• Est. Priority Date: 05/26/2004
• Status: Expired due to Fees

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chou, Chung-Cheng
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US10/854,051
• Time in Patent Office: 517 Days
• Field of Search: 365/222, 365/230.03
• US Class Current: 365/222
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays
• CPC Class Codes: G11C 2211/4061 Calibration or ate or cycle tuning

Abstract

A method and circuits are disclosed for refreshing a memory module. After receiving a refresh address identifying a word line to be refreshed, the refresh address is located in one of a predetermined number of memory blocks of the memory module that is monitored. It is further determined whether the word line has been accessed while the memory block is being monitored. If it is determined that the word line has not been accessed, the word line is refreshed. If it is determined that the word line has been accessed, the refreshing operation is skipped for that word line.

Claims

1. A method for refreshing a memory module comprising:

receiving a refresh address identifying a word line to be refreshed;

locating the refresh address in one of a predetermined number of memory blocks of the memory module that is monitored;

determining whether the word line has been accessed while the memory block is being monitored; and

refreshing the word line if it is determined that the word line has not been accessed, while skipping the refreshing if it is determined that the word line has been accessed.

2. The method of claim 1 further comprising dividing the memory module into the predetermined number of blocks based on a total number of bits available for an access address.

3. The method of claim 2 wherein the memory module is divided into memory blocks identifiable by a first number of bits with each block having a plurality of word lines identifiable by a second number of bits, wherein the sum of the first and second number of bits equals the total number of bits provided by the access address.

4. The method of claim 3 wherein the locating further includes determining the memory blocks by comparing the first number of bits, of the access address, with a corresponding number of bits, of the refresh address.

5. The method of claim 4 wherein the first number of bits are the most significant bits of the access address, and the corresponding number of bits of the refresh address are also the most significant bits thereof.

6. The method of claim 1 wherein the determining further includes monitoring whether each word line has been charged.

7. The method of claim 6 wherein the monitoring further includes using a status flag to represent whether a word line has been accessed.

8. The method of claim 1 further comprising storing an access address when the word line is accessed for later comparing with the refresh address.

9. A circuit for refreshing a memory module comprising:

a memory block location module for receiving a refresh address identifying a word line to be refreshed and for locating the refresh address in one of a predetermined number of memory blocks of the memory module; and

an evaluation module for determining whether the word line has been accessed during a time period in which the located memory block is monitored,

wherein the word line is refreshed if it is determined that it has not been accessed, while skipping the refreshing if it is determined that the word line has been accessed during the time period.

10. The circuit of claim 9 wherein the memory module is divided into the predetermined number of blocks based on a total number of bits available for the refresh address of the memory module.

11. The circuit of claim 10 wherein the memory module is divided into memory blocks identifiable by a first number of most significant bits, with each block having a plurality of word lines identifiable by a second number of bits, wherein the first and second number of bits make up the refresh address.

12. The circuit of claim 11 wherein the memory block location module further includes means for comparing the first number of bits of the refresh address with a corresponding number of bits of an access address.

13. The circuit of claim 11 wherein the second number of bits are the least significant bits of the refresh address.

14. The circuit of claim 9 wherein the evaluation module further includes at least one status flag associated with a word line for monitoring whether the word line has been accessed.

15. The circuit of claim 9 further comprising a storage module for storing one or more access addresses when a word line is accessed.

16. A method for refreshing a memory module comprising:

dividing the memory module into one or more memory blocks;

monitoring the memory blocks sequentially during a refresh operation of the memory module, wherein while conducing the refresh operation;

receiving a refresh address identifying a word line in a monitored memory block to be refreshed;

determining whether the word line has been accessed while the memory block is being monitored; and

refreshing the word line if it is determined that the word line has not been accessed, while skipping the refreshing, if it is determined that the word line has been accessed.

17. The method of claim 16 wherein the memory module is divided into memory blocks identifiable by a first number of most significant bits with each block having a plurality of word lines identifiable by a second number of bits, wherein the first and second number of bits make up the access address.

18. The method of claim 17 wherein the determining further includes determining whether word line of the access address is within the monitored memory block by comparing with the first number of most significant bits of the refresh address.

19. The method of claim 16 wherein the determining further includes monitoring whether each word line has been accessed using a status flag.

20. The method of claim 16 further comprising storing an access address when the word line is accessed for later comparing with the refresh address.