High-performance, superscalar-based computer system with out-of-order instruction execution

• US 6,959,375 B2
• Filed: 10/29/2002
• Issued: 10/25/2005
• Est. Priority Date: 07/08/1991
• Status: Expired due to Fees

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Wang, Johannes, Wang, Sze-Shun, Nguyen, Le Trong, Miyayama, Yoshiyuki, Trang, Quang H., Lau, Te-Li, Garg, Sanjiv, Lentz, Derek J., Hagiwara, Yasuaki
• Primary Examiner(s): Pan, Daniel H.
• Application Number:
  US10/282,045
• Publication Number:
  US 20030056086A1
• Time in Patent Office: 1,092 Days
• Field of Search: 712/23, 712/245, 712/206, 712/215, 712/212, 712/213, 712/214, 712/41, 711/125, 711/148
• US Class Current: 712/23
• CPC Class Codes: G06F 9/30054 Unconditional branch instructions
• CPC Class Codes: G06F 9/30061 Multi-way branch instructions, e.g. CASE
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/30116 Shadow registers, e.g. coupled registers, not forming part of the register space
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/30134 Register stacks; shift registers
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/323 for indirect branch instructions
• CPC Class Codes: G06F 9/327 for interrupts
• CPC Class Codes: G06F 9/38 Concurrent instruction execution, e.g. pipeline or look ahead
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3804 for branches, e.g. hedging, branch folding
• CPC Class Codes: G06F 9/3806 using address prediction, e.g. return stack, branch history buffer
• CPC Class Codes: G06F 9/3822 Parallel decoding, e.g. parallel decode units
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/384 : Register renaming
• CPC Class Codes: G06F 9/3851 : from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3854 : Instruction completion, e.g. retiring, committing or graduating
• CPC Class Codes: G06F 9/3856 : Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 : Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3863 : using multiple copies of the architectural state, e.g. shadow registers
• CPC Class Codes: G06F 9/3865 : using deferred exception handling, e.g. exception flags
• CPC Class Codes: G06F 9/3885 : using a plurality of independent parallel functional units

Abstract

A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

Claims

1. A superscalar microprocessor, comprising:

a fetch circuit to fetch a plurality of instructions from an instruction store, said plurality of instructions being in a program order;

a first in first out (FIFO) buffer to buffer said plurality of instructions from said fetch circuit;

a dispatch circuit to concurrently decode and concurrently dispatch more than one of said plurality of instructions buffered by said FIFO buffer; and

an execution unit, comprising;

a plurality of functional units, each of said plurality of functional units executing one of said plurality of instructions dispatched by said dispatch circuit out of said program order; and

a register file comprising temporary registers for temporarily storing out-of-order execution results from said plurality of functional units and a register array for storing results retired from said temporary registers, wherein said register file concurrently provides data to more than one of said plurality of functional units thereby enabling concurrent execution of more than one of said plurality of instructions by said plurality of functional units.

2. The microprocessor of claim 1, further comprising:

retirement circuitry that retires a plurality of said out-of-order executed instructions in program order by transferring said results of said out-of-order executed instructions from said temporary registers to said register array.

3. The microprocessor of claim 2, wherein said retirement circuitry is capable of retiring up to four instructions in a processor cycle.

4. The microprocessor of claim 1, wherein said FIFO buffer is capable of providing four or more instructions to said dispatch circuit in a processor cycle.

5. The microprocessor of claim 1, wherein said dispatch circuit is capable of dispatching up to four instructions to said execution unit in a processor cycle.

6. The microprocessor of claim 1, wherein said FIFO buffer includes first and second registers;

and

wherein each of said first and second registers concurrently provides one or more instructions to said dispatch circuit.

7. The microprocessor of claim 1, wherein said FIFO buffer includes first and second registers;

and

wherein each of said first and said second registers concurrently provides instruction sets of four instructions to said dispatch circuit.

8. The microprocessor of claim 1, wherein said dispatch circuit additionally includes circuitry for issuing said instructions out of program order to said execution units subject to the availability of said plurality of functional units.

9. The microprocessor of claim 1, wherein said instruction store is coupled to an external cache.

10. The microprocessor of claim 1, wherein said dispatch circuit concurrently dispatches said instructions by providing a plurality of said buffered instructions to said execution unit in a processor cycle.