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High-performance, superscalar-based computer system with out-of-order instruction execution

  • US 6,959,375 B2
  • Filed: 10/29/2002
  • Issued: 10/25/2005
  • Est. Priority Date: 07/08/1991
  • Status: Expired due to Fees
First Claim
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1. A superscalar microprocessor, comprising:

  • a fetch circuit to fetch a plurality of instructions from an instruction store, said plurality of instructions being in a program order;

    a first in first out (FIFO) buffer to buffer said plurality of instructions from said fetch circuit;

    a dispatch circuit to concurrently decode and concurrently dispatch more than one of said plurality of instructions buffered by said FIFO buffer; and

    an execution unit, comprising;

    a plurality of functional units, each of said plurality of functional units executing one of said plurality of instructions dispatched by said dispatch circuit out of said program order; and

    a register file comprising temporary registers for temporarily storing out-of-order execution results from said plurality of functional units and a register array for storing results retired from said temporary registers, wherein said register file concurrently provides data to more than one of said plurality of functional units thereby enabling concurrent execution of more than one of said plurality of instructions by said plurality of functional units.

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