Reconfigurable processing system and method

• US 6,959,378 B2
• Filed: 11/02/2001
• Issued: 10/25/2005
• Est. Priority Date: 11/06/2000
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Williams, Mark, Nickolls, John R., Madar, Lawrence J. III, Johnson, Scott D., Mirsky, Ethan, Pant, Amrit Raj, Kirthiranjan, Kambdur
• Primary Examiner(s): TSAI, HENRY
• Application Number:
  US10/004,246
• Publication Number:
  US 20020087846A1
• Time in Patent Office: 1,453 Days
• Field of Search: 712/229, 712/24, 712/2, 712/10, 712/15, 712/226
• US Class Current: 712/229
• CPC Class Codes: G06F 15/8061 Details on data memory access
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/325 for loops, e.g. loop detection or loop counter
• CPC Class Codes: G06F 9/345 of multiple operands or results addressing multiple banks G06F12/06
• CPC Class Codes: G06F 9/3455 using stride

Abstract

A reconfigurable processing system executes instructions and configurations in parallel. Initially, a first instruction loads configurations into configuration registers. The configuration field of a subsequently fetched instruction selects a configuration register. The instruction controls and controls of the configuration in the selected configuration register are decoded and modified as specified by the instruction. The controls provide data operands to the execution units which process the operands and generate results. Scalar data, vector data, or a combination of scalar and vector data can be processed. The processing is controlled by instructions executed in parallel with configurations invoked by configuration fields within the instructions. Vectors are processed using a vector register file which stores vectors. A vector address unit identifies addresses of vector elements in the vector register file to be processed. For each vector, vector address units provide addresses which stride through each element of each vector.

Claims

1. A method of controlling a reconfigurable processor, comprising:

executing a first instruction that loads a configuration into a configuration register;

executing a second instruction that references the configuration register; and

executing the configuration in the configuration register referenced by the second instruction, wherein executing the first instruction loads a plurality of configurations into respective configuration registers, wherein one of the plurality of configurations is loaded into a configuration register, and wherein the configuration and the first instruction are stored in a memory, and wherein the first instruction includes a displacement field indicating a location in the memory of the configuration relative to the first instruction.

2. The method of claim 1, wherein executing the first instruction loads a plurality of configurations into respective configuration registers, wherein one of the plurality of configurations is loaded into a configuration register.

3. The method of claim 1, wherein an application program issues the first instruction.

4. The method of claim 1, wherein a compiler generates the first instruction.

5. The method of claim 1, wherein executing the second instruction and the configuration further comprises retrieving operands requested by the second instruction and the configuration.

6. The method of claim 5, wherein the second instruction provides the operands to the configuration.

7. The method of claim 5, wherein a register provides the operands to the configuration.

8. The method of claim 5, wherein the second instruction includes an immediate value field, the second instruction being executed with values stored in the immediate value field.

9. The method of claim 5, wherein the second instruction includes an immediate value field, the configuration being executed with values stored in the immediate value field.

10. The method of claim 1, further comprising:

decoding controls from the second instruction and the configuration; and

processing data according to the decoded controls with one or more execution units in parallel.

11. The method of claim 10, further comprising generating one or more results with the one or more execution units.

12. The method of claim 11, further comprising writing the one or more results to a register.

13. The method of claim 11, further comprising storing the one or more results to a memory.

14. The method of claim 11, further comprising providing the one or more results to respective execution units.

15. The method of claim 1, further comprising pre-loading a second configuration register with a configuration while the configuration previously loaded in the first configuration register executes.

16. The method of claim 1, further comprising stalling the second instruction while the referenced configuration register is being loaded with a configuration.

17. The method of claim 1, wherein the first instruction, the second instruction, and the configuration are executed as part of an application program.

18. The method of claim 1, wherein executing the second instruction and the configuration includes performing an operation on scalar data.

19. The method of claim 1, wherein executing the second instruction and the configuration includes performing an operation on vector data.

20. The method of claim 1, wherein executing the second instruction and the includes performing an operation on scalar data and performing an operation on vector data.

21. A processing system, comprising:

means for executing a first instruction that loads a configuration into a configuration register; and

means for decoding a second instruction and the configuration, the second instruction referencing the configuration register containing the configuration

means for executing the second instruction and the configuration in parallel, wherein one of the plurality of configurations is loaded into a configuration register, and wherein the configuration and the first instruction are stored in a memory, and wherein the first instruction includes a displacement field indicating a location in the memory of the configuration relative to the first instruction.

22. A method of implementing a vector processing system, comprising:

executing a first instruction that loads a configuration into a configuration register;

executing a second instruction and a configuration stored in a configuration register referenced by the second instruction;

processing elements of a first vector according to the second instruction and the configuration, wherein

a vector register stores elements of the first vector, and

a vector address unit provides an address to the vector register which stores the first vector elements selected by the second instruction and the configuration.

23. The method of claim 22, wherein processing elements of the first vector further comprises writing data to the identified address through a write port of the vector register file.

24. The method of claim 22, wherein processing elements of the first vector further comprises reading data from the identified address through a read port of the vector register file.

25. The method of claim 22, wherein processing elements of the first vector further comprises:

initializing a current address of the first vector with a start address;

processing a first element of the first vector referenced by the current address with the instruction and configuration.

26. The method of claim 25, further comprising:

incrementing the current address with an address stride, wherein the incremented current address represents an address of a second element of the first vector; and

processing the second element referenced by the incremented current address.

27. The method of claim 26, for each successive element of the first vector, further comprising:

incrementing the previous current address with the address stride resulting in a new current address, wherein each successive new current address represents an address of a successive vector element; and

processing each successive vector element until all of the elements of the first vector have been processed.

28. The method of claim 27, further comprising identifying a start address of a second vector.

29. The method of claim 28, wherein identifying the start address of the second vector further comprises incrementing the start address of the first vector with a frame stride resulting in a second start address, wherein an initial value of a current address comprises the second start address.

30. The method of claim 29, further comprising processing the vector element referenced by the current address of the second vector.

31. The method of claim 30, for each successive vector element of the second vector, further comprising:

incrementing the previous current address with the address stride resulting in a new current address, wherein each successive new current address represents an address of a successive vector element of the second vector; and

processing each successive vector element until all of the elements of the second vector have been processed.

32. The method of claim 31, for each vector to be processed, further comprising:

identifying a start address of the vector;

processing a first element of the vector;

processing remaining successive elements of the vector by

incrementing the current address with an address stride resulting in successive current addresses;

processing corresponding successive elements referenced by the successive current addresses; and

after all of the elements of the vector have been processed, incrementing the start address by the frame stride to identify a start address of the next vector to be processed.

33. The method of claim 22, wherein a vector of data elements is loaded into the vector file prior to execution of the second instruction and the configuration.

34. The method of claim 22, wherein a vector of data elements is loaded into the vector file in parallel with execution of the second instruction and the configuration.

35. The method of claim 34, wherein the first instruction operates to process the first vector element by element by interlocking between the load port of the vector register file and the vector computation to process each element when it arrives in the vector register file.