Pitcher-shaped active area for field effect transistor and method of forming same

• US 6,960,514 B2
• Filed: 03/18/2004
• Issued: 11/01/2005
• Est. Priority Date: 10/26/2001
• Status: Expired due to Fees

• Current Assignee: Infineon Technologies AG
• Original Assignee: International Business Machines Corporation
• Inventors: Faltermeier, Johnathan, Heenan, Carol J., Sudo, Akira, Flaitz, Philip L., Jammy, Rajarao, Gluschenkov, Oleg, Beintner, Jochen, Kim, Byeong, Divakaruni, Rama, Takegawa, Yoichi, Seitz, Mihel
• Primary Examiner(s): FOURSON III, GEORGE R
• Application Number:
  US10/803,395
• Publication Number:
  US 20040173858A1
• Time in Patent Office: 593 Days
• Field of Search: 438/424, 438/701, 438/FOR.227
• US Class Current: 438/424
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264

Abstract

An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.

Claims

1. A pitcher-shaped active area structure for a field effect transistor (FET) comprising:

a semiconductor substrate; and

at least two shallow trench insulator (STI) structures formed into the substrate that isolate the FET and define an active area structure, the active area structure comprising a widened top portion and a bottom portion, wherein the widened top portion has a larger width than the bottom portion.

2. The structure of claim 1 further comprising a pad oxide layer formed on the substrate, and wherein the at least two STI structures are formed into the substrate through the pad oxide layer, the at least two STI structures comprising an STI oxide liner and an STI oxide fill formed on the STI oxide liner.

3. The structure of claim 1, wherein the at least two STI structures comprise divots in top portions of side walls of the at least two STI structures into which the widened top portion of the active area structure extends.

4. The structure of claim 3, wherein the semiconductor substrate comprises silicon, and wherein the widened top portion formed into divots comprises single crystalline silicon.

5. The structure of claim 3, wherein the divots comprise a depth of approximately 500 Å

or less.

6. The structure of claim 1, wherein the widened top portion of the active area structure further comprises rounded top corners.

7. The structure of claim 6, wherein the widened top portion of the active area structure includes a pad oxide layer that is in direct mechanical contact with the at least two STI structures.

8. The structure of claim 7, further comprising a gate conductor layer on the pad oxide layer and on the at least two STI structures, wherein the gate conductor layer is in direct mechanical contact with the pad oxide layer and the at least two STI structures.

9. The structure of claim 3, wherein the STI structures comprise insulation, wherein the divots define recesses below a top surface of the substrate and below a top surface of the insulation, and wherein the recesses have boundaries formed by the top portions of the side walls and by exterior surfaces of the insulation.

10. The structure of claim 9, wherein the widened top portion of the active area structure further comprises rounded top corners.

11. The structure of claim 10, wherein the widened top portion of the active area structure includes a pad oxide layer that is in direct mechanical contact with the at least two STI structures.

12. The structure of claim 11, further comprising a gate conductor layer on the pad oxide layer and on the at least two STI structures, wherein the gate conductor layer is in direct mechanical contact with the pad oxide layer and the at least two STI structures.