High-voltage semiconductor component

• US 6,960,798 B2
• Filed: 06/06/2003
• Issued: 11/01/2005
• Est. Priority Date: 09/02/1998
• Status: Expired due to Term

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies AG
• Inventors: Rueb, Michael, Strack, Helmut, Deboy, Gerald, Weber, Hans Martin, Ahlers, Dirk
• Primary Examiner(s): Wilson, Allan R.
• Application Number:
  US10/455,842
• Publication Number:
  US 20040007736A1
• Time in Patent Office: 879 Days
• Field of Search: 257/285, 257/287
• US Class Current: 257/285
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7801 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region lateral high-voltage MISFETs with channel well and drain offset region H01L29/7835
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236

Abstract

A semiconductor component has a semiconductor body comprising a blocking pn junction, a source zone of a first conductivity type connected to a first electrode and bordering on a zone forming the blocking pn junction of a second conductivity type complementary to the first conductivity type, and a drain zone of the first conductivity type connected to a second electrode. The side of the zone of the second conductivity type facing the drain zone forms a first surface, and in the region between the first surface and a second surface located between the first surface and the drain zone, comprises areas of the first and second conductivity type nested in one another. The second surface is positioned at a distance from the drain zone such that the areas of the first and second conductivity type nested in each other do not reach the drain zone.

Claims

1. Semiconductor component having a semiconductor body comprising a blocking pn junction, a source zone of a first conductivity type connected to a first electrode and bordering on a zone forming the blocking pn junction of a second conductivity type complementary to the first conductivity type, and a drain zone of the first conductivity type connected to a second electrode, the side of the zone of the second conductivity type facing the drain zone forming a first surface, and in the region between the first surface and a second surface located between the first surface and the drain zone, areas of the first and second conductivity type nested in one another, wherein the second surface is positioned at a distance from the drain zone such that the areas of the first and second conductivity type nested in each other do not reach the drain zone.

2. Semiconductor device according to claim 1, wherein a lightly doped region of the first conductivity type is provided between the second surface and the drain zone.

3. Semiconductor device according to claim 1, wherein the lightly doped region between the second surface and the drain zone is at least partly depleted when applying a blocking voltage.

4. Semiconductor device according to claim 1, wherein a degree of compensation effected by means of the doping in the areas of the first and second conductivity types has a monotonic course between the first and second surface.

5. Semiconductor device according to claim 4, wherein the degree of compensation has a stepped course.

6. Semiconductor device according to claim 1, wherein the first conductivity type is the n-conductivity type.

7. Semiconductor device according to claim 1, wherein the areas of the first and second conductivity types are arranged laterally in the semiconductor body.

8. Semiconductor device according to claim 1, wherein the areas of the first and second conductivity type are arranged vertically in the semiconductor body.

9. Semiconductor device according to claim 6, wherein in the areas of the second conductivity type a degree of compensation effected by means of doping is varied such that near the first surface acceptor impurities dominate and near the second surface donor impurities dominate.

10. Semiconductor device according to claim 1, wherein the areas of the second conductivity type have a roughly circular cross-section in a section parallel to the first surface and to the second surface and assume hexagonal surface packing.

11. Semiconductor device according to claim 1, wherein the areas of the second conductivity type have a roughly circular cross-section in a section parallel to the first surface and to the second surface and assume roughly square surface packing.

12. Semiconductor device according to claim 1, wherein the areas of the second conductivity type have a roughly strip-shaped cross-section in a section parallel to the first surface and to the second surface.

13. Semiconductor device according to claim 1, wherein a plurality of floating zones of the first and second conductivity type is provided.

14. Semiconductor device according to claim 13, wherein the floating zones form in the edge region of the semiconductor device a high-voltage resistant basic structure, and the floating zones are separated by intermediate zones of the first conductivity type, whereby the sum of the widths of one of the floating zone and one of the intermediate zone is smaller than the sum of the widths of one of the area of the first conductivity type and one of the areas of the second conductivity type and the charge carriers of the floating zones and the intermediate zones are completely cleared with the application of blocking voltage.

15. Semiconductor device according to claim 14, wherein at least one space charge region stopper is provided on the outermost edge of the edge termination of the semiconductor device.

16. Semiconductor device according to claim 15, wherein the space charge region stopper has a heavily doped zone of the first conductivity type arranged at or near the first surface and the second surface.

17. Semiconductor device according to claim 16, wherein the space charge region stopper has a damage implanted area.

18. Semiconductor device according to claim 17, wherein the space charge region stopper has a metal or a polysilicon containing electrode which is connected to the semiconductor body.