Low capacitance ESD protection device, and integrated circuit including the same

• US 6,960,811 B2
• Filed: 08/30/2004
• Issued: 11/01/2005
• Est. Priority Date: 11/07/2002
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Jian-Hsing, Wu, Yi-Hsun
• Primary Examiner(s): Smoot, Stephen W.
• Application Number:
  US10/929,735
• Publication Number:
  US 20050082618A1
• Time in Patent Office: 428 Days
• Field of Search: 257/355, 257/357, 257/360, 257/361
• US Class Current: 257/361
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements

Abstract

A low capacitance ESD protection device. The device comprises a substrate, a well of a first conductivity type in the substrate, a first and second transistor of the first conductivity type respectively on two sides of the well, a guard ring of a second conductivity type in the substrate, surrounding the well, and the first and second transistor, and a doped region of the second conductivity type in the well, wherein profiles of a drain and source region of each of the first and second transistor are un-symmetrical, and an area of the drain region is smaller than that of the source region in each of the first and second transistor.

Claims

1. A low capacitance ESD protection device comprising:

a substrate;

a well of a first conductivity type in the substrate;

a first and second transistor of the first conductivity type respectively on two sides of the well;

a guard ring of a second conductivity type in the substrate, surrounding the well, and the first and second transistor; and

a doped region of the second conductivity type in the well;

a conducting layer on the doped region, having a first, second and third portion separated from each other by gaps extend in a predetermined direction;

wherein, for each of the first and second transistor, a width of a drain region is substantially equal to that of a source region, and a length of the drain region is shorter than that of the source region.

2. The ESD protection device as claimed in claim 1 further comprising a second guard ring of the first conductivity type in the substrate, surrounding the guard ring of the second conductivity type.

3. The ESD protection device as claimed in claim 2, wherein the second guard ring is coupled to receive a first voltage level.

4. The ESD protection device as claimed in claim 1, wherein the first, second and third portion are respectively coupled to a pad, the drain region of the first transistor and the drain region of the second transistor.

5. The ESD protection device as claimed in claim 1, wherein the conducting layer is a silicide layer.

6. The ESD protection device as claimed in claim 1, wherein the doped region, and the drain regions of the first and second transistor are coupled to a pad, and the guard ring, and the source regions of the first and second transistor are coupled to receive a second voltage level.

7. The ESD protection device as claimed in claim 1, wherein the first and second conductivity type are N and P type, respectively.

8. The ESD protection device as claimed in claim 1, wherein, for each of the first and second transistor, a distance between the source region and the well is shorter than that between the drain region and the well.

9. The ESD protection device as claimed in claim 1, wherein, for each of the first and second transistor, a distance between the drain region and the well is shorter than that between the source region and the well.

10. The ESD protection device as claimed in claim 1, wherein, for each of the first and second transistor, a gate extends in the predetermined direction.

11. The ESD protection device as claimed in claim 1, wherein, for each of the first and second transistor, a gate extends substantially perpendicular to the predetermined direction.

12. The ESD protection device as claimed in claim 1, wherein gates of the first and second transistor are in alignment.

13. The ESD protection device as claimed in claim 1, wherein gates of the first and second transistor extend in different directions.

14. An integrated circuit comprising:

a core circuit; and

a low capacitance ESD protection device protecting the core circuit form ESD damages, comprising;

a substrate;

a well of a first conductivity type in the substrate;

a first and second transistor of the first conductivity type respectively on two sides of the well;

a guard ring of a second conductivity type in the substrate, surrounding the well, and the first and second transistor; and

a doped region of the second conductivity type in the well;

a conducting layer on the doped region, having a first, second and third portion separated from each other by gaps extend in a predetermined direction;

wherein profiles of a drain and source region of each of the first and second transistor are un-symmetrical, and an area of the drain region is smaller than that of the source region in each of the first and second transistor.

15. The integrated circuit as claimed in claim 14, wherein the low capacitance ESD protection device further comprises a second guard ring of the first conductivity type in the substrate, surrounding the guard ring of the second conductivity type.

16. The integrated circuit as claimed in claim 15, wherein the second guard ring is coupled to receive a first voltage level.

17. The integrated circuit as claimed in claim 14, wherein the first, second and third portion are respectively coupled to a pad, the drain region of the first transistor and the drain region of the second transistor.

18. The integrated circuit as claimed in claim 14, wherein the conducting layer is a silicide layer.

19. The integrated circuit as claimed in claim 14, wherein the first and second conductivity type are N and P type respectively.

20. The integrated circuit as claimed in claim 14, wherein, for each of the first and second transistor, a distance between the source region and the well is shorter than that between the drain region and the well.

21. The integrated circuit as claimed in claim 14, wherein, for each of the first and second transistor, a distance between the drain region and the well is shorter than that between the source region and the well.

22. The integrated circuit as claimed in claim 14, wherein, for each of the first and second transistor, a gate extends in the predetermined direction.

23. The integrated circuit as claimed in claim 14, wherein, for each of the first and second transistor, a gate extends substantially perpendicular to the predetermined direction.

24. The integrated circuit as claimed in claim 14, wherein gates of the first and second transistor are in alignment.

25. The integrated circuit as claimed in claim 14, wherein gates of the first and second transistor extend in different directions.